JPS5528122A - Control system for multiplex system - Google Patents

Control system for multiplex system

Info

Publication number
JPS5528122A
JPS5528122A JP9941078A JP9941078A JPS5528122A JP S5528122 A JPS5528122 A JP S5528122A JP 9941078 A JP9941078 A JP 9941078A JP 9941078 A JP9941078 A JP 9941078A JP S5528122 A JPS5528122 A JP S5528122A
Authority
JP
Japan
Prior art keywords
cpu
route
unit
cpucc
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9941078A
Other languages
Japanese (ja)
Inventor
Shinji Tachika
Hiroshi Shintani
Katsuhiko Yazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
NTT Inc
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP9941078A priority Critical patent/JPS5528122A/en
Publication of JPS5528122A publication Critical patent/JPS5528122A/en
Pending legal-status Critical Current

Links

Landscapes

  • Information Transfer Systems (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To enable to set the route from CPU to external unit simply, by providing the data channel crossing part to set the route of CPU with the external unit of the system itself, and another system corresponding to CPU.
CONSTITUTION: A CPU, e.g., CCo has a plurality of external units I/O connected to it via the channel bus CBo to control the route control flip flop FFo corresponding to CPU. Further, the data channel crossing section DCCo controlled with the route control FF1 corresponding to CPUCC1 in another system and having the gate to set the route of CPUCCo and the unit I/O of the system itself and another system, is provided corresponding to CPUCCo. Thus, the unit I/O of the system in which the control FF is "1" can use only CCo of CPU of the system itself, and the unit I/O in which the controll FF is "0" can use only CPUCC1 in another system, to simplify the setting of route from CPU to the unit I/O.
COPYRIGHT: (C)1980,JPO&Japio
JP9941078A 1978-08-14 1978-08-14 Control system for multiplex system Pending JPS5528122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9941078A JPS5528122A (en) 1978-08-14 1978-08-14 Control system for multiplex system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9941078A JPS5528122A (en) 1978-08-14 1978-08-14 Control system for multiplex system

Publications (1)

Publication Number Publication Date
JPS5528122A true JPS5528122A (en) 1980-02-28

Family

ID=14246702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9941078A Pending JPS5528122A (en) 1978-08-14 1978-08-14 Control system for multiplex system

Country Status (1)

Country Link
JP (1) JPS5528122A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5533214A (en) * 1978-08-31 1980-03-08 Oki Electric Ind Co Ltd Information processing system
JPS57162890A (en) * 1981-03-31 1982-10-06 Teac Co Information signal recorder
JPS6486327A (en) * 1988-08-19 1989-03-31 Teac Corp Information signal recorder

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504298A (en) * 1973-05-16 1975-01-17
JPS5058954A (en) * 1973-09-26 1975-05-22
JPS50124547A (en) * 1974-03-18 1975-09-30

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS504298A (en) * 1973-05-16 1975-01-17
JPS5058954A (en) * 1973-09-26 1975-05-22
JPS50124547A (en) * 1974-03-18 1975-09-30

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5533214A (en) * 1978-08-31 1980-03-08 Oki Electric Ind Co Ltd Information processing system
JPS57162890A (en) * 1981-03-31 1982-10-06 Teac Co Information signal recorder
JPS6486327A (en) * 1988-08-19 1989-03-31 Teac Corp Information signal recorder

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