JPS553038A - Microprogram control unit - Google Patents

Microprogram control unit

Info

Publication number
JPS553038A
JPS553038A JP7502278A JP7502278A JPS553038A JP S553038 A JPS553038 A JP S553038A JP 7502278 A JP7502278 A JP 7502278A JP 7502278 A JP7502278 A JP 7502278A JP S553038 A JPS553038 A JP S553038A
Authority
JP
Japan
Prior art keywords
memory
control unit
microorder
microprogram
via bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7502278A
Other languages
Japanese (ja)
Inventor
Harunobu Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7502278A priority Critical patent/JPS553038A/en
Publication of JPS553038A publication Critical patent/JPS553038A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To shorten the execution time of the microprogram by providing the data buffer between the memory storing the microorder and the microprogram control circuit.
CONSTITUTION: The control unit consists of the following units: address register 1; memory 2 storing the microorder; microprogram control circuit 3; data buffer 4 and 5 into which the order of plural words read out through one memory access is stored via bus a23 from memory 2; data buffer control circuit 6 which draws out the order from buffer 4 and 5 by one word and then sends them to circuit 3 via bus a63; and others. With such constitution of the control unit, machine cycle A, contents B of the address register and the signals of execution cycle C are applied in the form of the operation timing to carry out the microorder, and timing signal D and E are applied to buffer 4 and 5 via bus a23. In such way, the lowering of the process capacity can be avoided even with use of the memory featuring the slow time cycle.
COPYRIGHT: (C)1980,JPO&Japio
JP7502278A 1978-06-20 1978-06-20 Microprogram control unit Pending JPS553038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7502278A JPS553038A (en) 1978-06-20 1978-06-20 Microprogram control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7502278A JPS553038A (en) 1978-06-20 1978-06-20 Microprogram control unit

Publications (1)

Publication Number Publication Date
JPS553038A true JPS553038A (en) 1980-01-10

Family

ID=13564130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7502278A Pending JPS553038A (en) 1978-06-20 1978-06-20 Microprogram control unit

Country Status (1)

Country Link
JP (1) JPS553038A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5826997U (en) * 1981-08-19 1983-02-21 荏原インフイルコ株式会社 biological treatment equipment
JPS6171891A (en) * 1984-09-13 1986-04-12 Shimizu Constr Co Ltd Fluidized bed bioreactor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5826997U (en) * 1981-08-19 1983-02-21 荏原インフイルコ株式会社 biological treatment equipment
JPS6171891A (en) * 1984-09-13 1986-04-12 Shimizu Constr Co Ltd Fluidized bed bioreactor

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