JPS5567985A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5567985A
JPS5567985A JP14064378A JP14064378A JPS5567985A JP S5567985 A JPS5567985 A JP S5567985A JP 14064378 A JP14064378 A JP 14064378A JP 14064378 A JP14064378 A JP 14064378A JP S5567985 A JPS5567985 A JP S5567985A
Authority
JP
Japan
Prior art keywords
ram10
buffer
input
data
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14064378A
Other languages
Japanese (ja)
Inventor
Mitsutoshi Nagoya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14064378A priority Critical patent/JPS5567985A/en
Publication of JPS5567985A publication Critical patent/JPS5567985A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

PURPOSE: To store easily input-output information by providing a latch circuit between RAM and an input-output buffer.
CONSTITUTION: Access corresponding to address information processed through decoder 11 is attained to write data in RAM10 through input-output buffer 12 or to store temporarily data, read out from RAM10, in buffer 12. Those write and read data can easily be stored in latch circuit 13, provided between buffer 12 and RAM10, without using another data bus. Further, an external signal is stored in circuit 13 to attain register storage operation.
COPYRIGHT: (C)1980,JPO&Japio
JP14064378A 1978-11-15 1978-11-15 Information processor Pending JPS5567985A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14064378A JPS5567985A (en) 1978-11-15 1978-11-15 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14064378A JPS5567985A (en) 1978-11-15 1978-11-15 Information processor

Publications (1)

Publication Number Publication Date
JPS5567985A true JPS5567985A (en) 1980-05-22

Family

ID=15273433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14064378A Pending JPS5567985A (en) 1978-11-15 1978-11-15 Information processor

Country Status (1)

Country Link
JP (1) JPS5567985A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4858111A (en) * 1983-07-29 1989-08-15 Hewlett-Packard Company Write-back cache system using concurrent address transfers to setup requested address in main memory before dirty miss signal from cache

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4858111A (en) * 1983-07-29 1989-08-15 Hewlett-Packard Company Write-back cache system using concurrent address transfers to setup requested address in main memory before dirty miss signal from cache

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