JPS553077A - Multi-virtual data processing system - Google Patents

Multi-virtual data processing system

Info

Publication number
JPS553077A
JPS553077A JP7610078A JP7610078A JPS553077A JP S553077 A JPS553077 A JP S553077A JP 7610078 A JP7610078 A JP 7610078A JP 7610078 A JP7610078 A JP 7610078A JP S553077 A JPS553077 A JP S553077A
Authority
JP
Japan
Prior art keywords
entry
tlb
bit
data processing
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7610078A
Other languages
Japanese (ja)
Inventor
Takashi Sakai
Isao Aizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7610078A priority Critical patent/JPS553077A/en
Publication of JPS553077A publication Critical patent/JPS553077A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To avoid occurrence of the overhead in the multi-virtual data processing system by preserving the common region on TLB and then repealing the user region in case the virtual space is switched.
CONSTITUTION: For the entry on TLB, the display is given as V-bit "1" (effective) and C-bit "1" (common region). In case the virtual space is switched, the entry on TLB must be registered again. In this connection, the entries are once repealed collectively. In this case, however, the entry whose C-bit is "1" is made effective, and thus the entry corresponding to the common region is kept effective. Thus, the time can be saved more than when the registering is given again after all entries are repealed, avoiding occurrence of the overhead.
COPYRIGHT: (C)1980,JPO&Japio
JP7610078A 1978-06-23 1978-06-23 Multi-virtual data processing system Pending JPS553077A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7610078A JPS553077A (en) 1978-06-23 1978-06-23 Multi-virtual data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7610078A JPS553077A (en) 1978-06-23 1978-06-23 Multi-virtual data processing system

Publications (1)

Publication Number Publication Date
JPS553077A true JPS553077A (en) 1980-01-10

Family

ID=13595443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7610078A Pending JPS553077A (en) 1978-06-23 1978-06-23 Multi-virtual data processing system

Country Status (1)

Country Link
JP (1) JPS553077A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60112153A (en) * 1983-11-22 1985-06-18 Hitachi Ltd Controlling method of cache memory
JPS61101855A (en) * 1984-10-24 1986-05-20 Fujitsu Ltd Tlb controlling system in multiple virtual memory system
JP2013145599A (en) * 2004-07-30 2013-07-25 Intel Corp Maintaining processor resources during architectural events

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60112153A (en) * 1983-11-22 1985-06-18 Hitachi Ltd Controlling method of cache memory
JPS61101855A (en) * 1984-10-24 1986-05-20 Fujitsu Ltd Tlb controlling system in multiple virtual memory system
JP2013145599A (en) * 2004-07-30 2013-07-25 Intel Corp Maintaining processor resources during architectural events
JP2013257911A (en) * 2004-07-30 2013-12-26 Intel Corp Holding of processor resource between architecture events
JP2015084260A (en) * 2004-07-30 2015-04-30 インテル コーポレイション Processor and system
US9086958B2 (en) 2004-07-30 2015-07-21 Intel Corporation Maintaining processor resources during architectural events
US9152561B2 (en) 2004-07-30 2015-10-06 Intel Corporation Maintaining processor resources during architectural events
US9164901B2 (en) 2004-07-30 2015-10-20 Intel Corporation Maintaining processor resources during architectural events
US9164918B2 (en) 2004-07-30 2015-10-20 Intel Corporation Maintaining processor resources during architectural events
JP2016192241A (en) * 2004-07-30 2016-11-10 インテル コーポレイション Processor and system
US9507730B2 (en) 2004-07-30 2016-11-29 Intel Corporation Maintaining processor resources during architectural events
US9996475B2 (en) 2004-07-30 2018-06-12 Intel Corporation Maintaining processor resources during architectural events
JP2019050027A (en) * 2004-07-30 2019-03-28 インテル コーポレイション Processor
US10303620B2 (en) 2004-07-30 2019-05-28 Intel Corporation Maintaining processor resources during architectural events
US10740249B2 (en) 2004-07-30 2020-08-11 Intel Corporation Maintaining processor resources during architectural events

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