JPS5532161A - Integration processing unit - Google Patents

Integration processing unit

Info

Publication number
JPS5532161A
JPS5532161A JP10525278A JP10525278A JPS5532161A JP S5532161 A JPS5532161 A JP S5532161A JP 10525278 A JP10525278 A JP 10525278A JP 10525278 A JP10525278 A JP 10525278A JP S5532161 A JPS5532161 A JP S5532161A
Authority
JP
Japan
Prior art keywords
result data
intermediate result
unit
operator
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10525278A
Other languages
Japanese (ja)
Inventor
Keiichiro Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10525278A priority Critical patent/JPS5532161A/en
Publication of JPS5532161A publication Critical patent/JPS5532161A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To simplify the control mode, by inputting the two intermediate result data from the intermediate result data unit to the stage pipeline operator from the intermediate result data input section.
CONSTITUTION: The memory unit 1 stores the operand data of N+1 sets, and a plurality of stage pipeline operator 2 operates the operand data read out from the unit 1. The intermediate result data memory unit 3 storing the intermediate result data outputted from the operator 2 is provided, and the two intermediate result data of the r-th and s-th intermediate results are inprtted to the operator 2 via the input sections g3 and g4 from the unit 3. Further, the intermediate result data being the output from the operator 2 is stored in the unit 3 and it is used for next operation. Thus, the control mode can be simplified.
COPYRIGHT: (C)1980,JPO&Japio
JP10525278A 1978-08-29 1978-08-29 Integration processing unit Pending JPS5532161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10525278A JPS5532161A (en) 1978-08-29 1978-08-29 Integration processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10525278A JPS5532161A (en) 1978-08-29 1978-08-29 Integration processing unit

Publications (1)

Publication Number Publication Date
JPS5532161A true JPS5532161A (en) 1980-03-06

Family

ID=14402454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10525278A Pending JPS5532161A (en) 1978-08-29 1978-08-29 Integration processing unit

Country Status (1)

Country Link
JP (1) JPS5532161A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58181165A (en) * 1982-04-16 1983-10-22 Hitachi Ltd Vector operating processor
JPS60134975A (en) * 1983-12-24 1985-07-18 Fujitsu Ltd Arithmetic circuit of sum of products
JPS6123276A (en) * 1984-07-11 1986-01-31 Nec Corp Data processor
JPS61101872A (en) * 1984-10-24 1986-05-20 Sony Corp Fast fourier transform arithmetic circuit
JPS61160175A (en) * 1984-12-31 1986-07-19 Nec Corp Arithmetic unit for vector sum
JPS6222177A (en) * 1985-07-22 1987-01-30 Oki Electric Ind Co Ltd Digital signal processor
JPS6226579A (en) * 1985-07-26 1987-02-04 Nec Corp Vector sum-total arithmetic unit
JPS6267676A (en) * 1985-09-19 1987-03-27 Nec Corp Vector data processor
JPS6262372U (en) * 1986-10-02 1987-04-17
JPS6262373U (en) * 1986-10-02 1987-04-17
JPS63265366A (en) * 1987-04-23 1988-11-01 Sony Corp Multiplex arithmetic circuit for time base

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58181165A (en) * 1982-04-16 1983-10-22 Hitachi Ltd Vector operating processor
JPS60134975A (en) * 1983-12-24 1985-07-18 Fujitsu Ltd Arithmetic circuit of sum of products
JPS6123276A (en) * 1984-07-11 1986-01-31 Nec Corp Data processor
JPS61101872A (en) * 1984-10-24 1986-05-20 Sony Corp Fast fourier transform arithmetic circuit
JPS61160175A (en) * 1984-12-31 1986-07-19 Nec Corp Arithmetic unit for vector sum
JPS6222177A (en) * 1985-07-22 1987-01-30 Oki Electric Ind Co Ltd Digital signal processor
JPS6226579A (en) * 1985-07-26 1987-02-04 Nec Corp Vector sum-total arithmetic unit
JPS6267676A (en) * 1985-09-19 1987-03-27 Nec Corp Vector data processor
JPS6262372U (en) * 1986-10-02 1987-04-17
JPS6262373U (en) * 1986-10-02 1987-04-17
JPS63265366A (en) * 1987-04-23 1988-11-01 Sony Corp Multiplex arithmetic circuit for time base

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