JPS5534488A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

Info

Publication number
JPS5534488A
JPS5534488A JP10787278A JP10787278A JPS5534488A JP S5534488 A JPS5534488 A JP S5534488A JP 10787278 A JP10787278 A JP 10787278A JP 10787278 A JP10787278 A JP 10787278A JP S5534488 A JPS5534488 A JP S5534488A
Authority
JP
Japan
Prior art keywords
layer
crystal
single crystal
oxide membrane
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10787278A
Other languages
Japanese (ja)
Other versions
JPS5852345B2 (en
Inventor
Kunihiko Hirashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP53107872A priority Critical patent/JPS5852345B2/en
Publication of JPS5534488A publication Critical patent/JPS5534488A/en
Publication of JPS5852345B2 publication Critical patent/JPS5852345B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Landscapes

  • Static Random-Access Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To heighten the integration density by making multi-crystalized semiconductor layer into three dimention structure with electrode wiring layer, thru the method wherein the process of growing single crystal semiconductor and the process of forming multi-crystal semiconductor layer among the former semiconductor layers are repeated. CONSTITUTION:Oxide membrane 2 is left in stripe form on a p-type crystal semiconductor substrate 1, while an n-type single crystal silicon layer 3 of high density is epitaxial grown and are made as IGFET source. Oxide membrane 4 is thickly formed covering whole surface, multi-crystal Si layer 5 is laminated at gate position, which is polish finished until the polishing reaches the upper surface of oxide membrane 4 and is etched selectively. By repeating the above procedures, single crystal Si layers 3,6,9 are made into source channel drain region, and IGFET is constructed three dimentionally wherein thin oxide membranes 7 are made into gate insulation membranes and multi-crystal Si layer 8 are made into gate electrodes.
JP53107872A 1978-09-01 1978-09-01 Semiconductor device and its manufacturing method Expired JPS5852345B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53107872A JPS5852345B2 (en) 1978-09-01 1978-09-01 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53107872A JPS5852345B2 (en) 1978-09-01 1978-09-01 Semiconductor device and its manufacturing method

Publications (2)

Publication Number Publication Date
JPS5534488A true JPS5534488A (en) 1980-03-11
JPS5852345B2 JPS5852345B2 (en) 1983-11-22

Family

ID=14470217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53107872A Expired JPS5852345B2 (en) 1978-09-01 1978-09-01 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JPS5852345B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5837948A (en) * 1981-08-31 1983-03-05 Toshiba Corp Laminated semiconductor memory device
JPS5884456A (en) * 1981-10-27 1983-05-20 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Integrated circuit bipolar memory cell
JPS6461050A (en) * 1987-09-01 1989-03-08 Nec Corp Semiconductor storage device
JPH06260593A (en) * 1993-02-03 1994-09-16 Internatl Business Mach Corp <Ibm> Three-dimensional semiconductor and its preparation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5837948A (en) * 1981-08-31 1983-03-05 Toshiba Corp Laminated semiconductor memory device
JPS5884456A (en) * 1981-10-27 1983-05-20 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Integrated circuit bipolar memory cell
JPS6461050A (en) * 1987-09-01 1989-03-08 Nec Corp Semiconductor storage device
JPH06260593A (en) * 1993-02-03 1994-09-16 Internatl Business Mach Corp <Ibm> Three-dimensional semiconductor and its preparation

Also Published As

Publication number Publication date
JPS5852345B2 (en) 1983-11-22

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