JPS6467936A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6467936A
JPS6467936A JP62225026A JP22502687A JPS6467936A JP S6467936 A JPS6467936 A JP S6467936A JP 62225026 A JP62225026 A JP 62225026A JP 22502687 A JP22502687 A JP 22502687A JP S6467936 A JPS6467936 A JP S6467936A
Authority
JP
Japan
Prior art keywords
layer
silicon
semiconductor
implanted
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62225026A
Other languages
Japanese (ja)
Inventor
Tadashi Nishimura
Yoichi Akasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62225026A priority Critical patent/JPS6467936A/en
Publication of JPS6467936A publication Critical patent/JPS6467936A/en
Pending legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To form a semiconductor layer having high thickness accuracy of the layer, no remaining damage to its semiconductor main surface and high breakdown strength by forming a silicon oxide layer in a silicon substrate, and epitaxially growing one conductivity type silicon layer thereon adjacently. CONSTITUTION:After oxygen ions are implanted to a P-type silicon substrate 1 to form a silicon oxide layer 2 as a protective layer, a single crystalline silicon layer is formed by annealing on the surface, and a buried oxide film 3 is formed under the layer. Then, the layer 2 on the surface is removed, and an N<+> type epitaxially grown layer 4 is formed. Then, high concentration arsenic ions are implanted, the surface is well cleaned, and an N<-> type silicon layer 5 is grown. Thereafter, a step of processing a semiconductor is conducted to obtain a silicon island isolated by the same dielectric as that of a silicon island of a conventional insulating layer state. Since the semiconductor layer is epitaxially grown in this manner, the surface of the silicon layer is not polished and not accordingly damaged. Further, the thickness of the film is formed constantly.
JP62225026A 1987-09-08 1987-09-08 Manufacture of semiconductor device Pending JPS6467936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62225026A JPS6467936A (en) 1987-09-08 1987-09-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62225026A JPS6467936A (en) 1987-09-08 1987-09-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6467936A true JPS6467936A (en) 1989-03-14

Family

ID=16822901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62225026A Pending JPS6467936A (en) 1987-09-08 1987-09-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6467936A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114242647A (en) * 2021-12-08 2022-03-25 中环领先半导体材料有限公司 Method for improving thickness uniformity of device silicon layer of silicon wafer on insulator
WO2026003919A1 (en) * 2024-06-24 2026-01-02 Ntt株式会社 Strain introduction method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114242647A (en) * 2021-12-08 2022-03-25 中环领先半导体材料有限公司 Method for improving thickness uniformity of device silicon layer of silicon wafer on insulator
WO2026003919A1 (en) * 2024-06-24 2026-01-02 Ntt株式会社 Strain introduction method

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