JPS5534577A - Clock driver circuit - Google Patents
Clock driver circuitInfo
- Publication number
- JPS5534577A JPS5534577A JP10783978A JP10783978A JPS5534577A JP S5534577 A JPS5534577 A JP S5534577A JP 10783978 A JP10783978 A JP 10783978A JP 10783978 A JP10783978 A JP 10783978A JP S5534577 A JPS5534577 A JP S5534577A
- Authority
- JP
- Japan
- Prior art keywords
- logic
- output
- driver circuit
- inverters
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
- H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To shorten the rise time and decay time for pulses, enlarge output and reduce power consumption in a clock driver circuit by constituting the clock driver circuit by means of two inverter circuits and one transistor. CONSTITUTION:A clock input signal is entered into input terminal 1 and, when the input sides of inverters 5 and 6 are logic ''1'', the inside output transistors of inverters are connected and the output sides become logic ''0''. Therefore, transistor 7 is disconnected and output terminal 4 becomes logic ''0''. In case of no input clock signal, each operation is reversed, so that the logic of output terminal 4 becomes ''1''. in any status, any one of transistors, transistor 7 or transistors in inverters 5 and 6, is connected, so that the impedance in the output terminal 4 is reduced, the rise time and decay time for pulses are shorten and the constant collector current does not flow in the circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10783978A JPS5534577A (en) | 1978-09-02 | 1978-09-02 | Clock driver circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10783978A JPS5534577A (en) | 1978-09-02 | 1978-09-02 | Clock driver circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5534577A true JPS5534577A (en) | 1980-03-11 |
Family
ID=14469347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10783978A Pending JPS5534577A (en) | 1978-09-02 | 1978-09-02 | Clock driver circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5534577A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4767465B2 (en) * | 1999-10-15 | 2011-09-07 | ボルボ ラストバグナー アーベー | Brake disc for vehicle disc brake |
-
1978
- 1978-09-02 JP JP10783978A patent/JPS5534577A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4767465B2 (en) * | 1999-10-15 | 2011-09-07 | ボルボ ラストバグナー アーベー | Brake disc for vehicle disc brake |
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