JPS553604A - Packaging method of resistance element for integrated circuit - Google Patents

Packaging method of resistance element for integrated circuit

Info

Publication number
JPS553604A
JPS553604A JP7414478A JP7414478A JPS553604A JP S553604 A JPS553604 A JP S553604A JP 7414478 A JP7414478 A JP 7414478A JP 7414478 A JP7414478 A JP 7414478A JP S553604 A JPS553604 A JP S553604A
Authority
JP
Japan
Prior art keywords
resistance elements
terminals
integrated circuit
resistance element
hexangle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7414478A
Other languages
Japanese (ja)
Inventor
Sumio Imaoka
Susumu Sato
Kunihiko Hirashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP7414478A priority Critical patent/JPS553604A/en
Publication of JPS553604A publication Critical patent/JPS553604A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To provide easy slicing by reducing interconnection to a minimum by locating the respective terminals of each resistance around the centrel portion f a set of resistance elements when a set of resistance elements for a master slice is formed by use of a plurality of resistances. CONSTITUTION:When a set of resistance elements for a master slice is constructed with three diffusion resistance elements 1-3, the terminals A-C of each element are positioned in the lump around a central portion in such a manner that a hexangle is formed with six terminals. In such arrangement, the interconnection is accommodated within the hexangle, so that it is not necessary to bring then out. Accordingly, the slicing becomes easy and the degree of integration is greatly improved because useless areas, disconnection of wiring and generation of parasitic effect can be avoided.
JP7414478A 1978-06-21 1978-06-21 Packaging method of resistance element for integrated circuit Pending JPS553604A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7414478A JPS553604A (en) 1978-06-21 1978-06-21 Packaging method of resistance element for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7414478A JPS553604A (en) 1978-06-21 1978-06-21 Packaging method of resistance element for integrated circuit

Publications (1)

Publication Number Publication Date
JPS553604A true JPS553604A (en) 1980-01-11

Family

ID=13538677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7414478A Pending JPS553604A (en) 1978-06-21 1978-06-21 Packaging method of resistance element for integrated circuit

Country Status (1)

Country Link
JP (1) JPS553604A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6065629A (en) * 1983-09-20 1985-04-15 Fujitsu Ltd Resistor ladder circuit network
JPS6082601U (en) * 1983-11-11 1985-06-07 株式会社日立製作所 Airtight optical connector
JPS60112327A (en) * 1983-11-22 1985-06-18 Sharp Corp Digital/analog converter of mos integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6065629A (en) * 1983-09-20 1985-04-15 Fujitsu Ltd Resistor ladder circuit network
JPS6082601U (en) * 1983-11-11 1985-06-07 株式会社日立製作所 Airtight optical connector
JPS60112327A (en) * 1983-11-22 1985-06-18 Sharp Corp Digital/analog converter of mos integrated circuit

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