JPS5537628A - Bus multi-jump system - Google Patents

Bus multi-jump system

Info

Publication number
JPS5537628A
JPS5537628A JP10970778A JP10970778A JPS5537628A JP S5537628 A JPS5537628 A JP S5537628A JP 10970778 A JP10970778 A JP 10970778A JP 10970778 A JP10970778 A JP 10970778A JP S5537628 A JPS5537628 A JP S5537628A
Authority
JP
Japan
Prior art keywords
register
data
jump
address
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10970778A
Other languages
Japanese (ja)
Other versions
JPS6127776B2 (en
Inventor
Kunihiko Onuma
Hideo Maejima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10970778A priority Critical patent/JPS5537628A/en
Publication of JPS5537628A publication Critical patent/JPS5537628A/en
Publication of JPS6127776B2 publication Critical patent/JPS6127776B2/ja
Granted legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To realize multi-jump branch operation to various subroutines within an executive routine of instruction at a time, by using part or all of data on a data bus as an element (address of ROM) for the multi-jump operation.
CONSTITUTION: A control structure part is provided with jump data latch register 303 connected to data bus 201. With flag register 305 set, the contnets of register 303 are inputted to microprogram address generator 203A by data selector 304 to generate an address of jump data in register 303 and with register 305 reset, the contents of instruction register 202 are inputted by selector 304 to generate an address of an instruction in register 202. In this way, ROM address register 205 can set the contents of bus 201 and multi-jump operation corresponding to the contents of data on bus 201 becomes possible.
COPYRIGHT: (C)1980,JPO&Japio
JP10970778A 1978-09-08 1978-09-08 Bus multi-jump system Granted JPS5537628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10970778A JPS5537628A (en) 1978-09-08 1978-09-08 Bus multi-jump system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10970778A JPS5537628A (en) 1978-09-08 1978-09-08 Bus multi-jump system

Publications (2)

Publication Number Publication Date
JPS5537628A true JPS5537628A (en) 1980-03-15
JPS6127776B2 JPS6127776B2 (en) 1986-06-27

Family

ID=14517172

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10970778A Granted JPS5537628A (en) 1978-09-08 1978-09-08 Bus multi-jump system

Country Status (1)

Country Link
JP (1) JPS5537628A (en)

Also Published As

Publication number Publication date
JPS6127776B2 (en) 1986-06-27

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