JPS6127776B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention is based on data on a bus in a computer.
This invention relates to a bus multi-jump method that quickly determines a large number of jump destination addresses.

The control flow of a computer based on the microprogram method is performed by sequentially incrementing the designated address of the microprogram or resetting a new address (referred to as a jump). The control content changes depending on how this address branch is performed. As shown in FIG. 1, address branching in a conventional microprogram starts with an instruction fetch cycle that brings an instruction, and branches 12 to execution routines 13A to 13E for the fetched instruction. Generally, an instruction is stored in an instruction register (IR), and therefore, according to the contents of the IR, a branch is made to the beginning of a uniquely determined execution routine 13A to 13E for that instruction. However, in the execution routine of that instruction, for example 13E, the first processing routine 1
After 4A, it branches under various conditions. In this branch, for example, a judgment 1 is made as to whether the contents of a certain register are negative or not, and various judgments 15A, 15B, and 15C are followed, such as a certain process 14B if the content is negative, and another process 15B if it is zero. Processing 14
B, 14C, 14D, and 14E are being performed. In this method, when the number of judgment elements 15A to 15C increases, the number of judgment circuits increases, and a series of judgments are performed serially during a series of processes.
The judgment microprogram must be inserted many times, leading to a decrease in the instruction processing rate.
FIG. 2 shows a block diagram of a data structure section 215 (a section that transfers data and performs calculations) and a control structure section 216 (a section that performs control relations such as determining instructions and branching) of a conventional computer. As is clear from this figure, the data structure section 2
It is no exaggeration to say that the control structure section 216 and the control structure section 216 are almost neatly separated, and branching by instructions writes the instruction on the data bus 201 to the instruction register 202 in the control structure section 216. The contents of this register 202 are modified in various ways by the instruction decoder and encoder 203, and the contents are passed through the output buffer 204A to the ROM address register 204.
Set to 05. ROM address register 20
The content set to 5 is the content of the command with a modification added, and this modification can be added in any form convenient for various types of machines. ROM
206 uses the contents of this register 205 as an address and sets a corresponding plural-bit control signal in the microinstruction register 220, and then sends it to the decoder 214. Decoder 214
The control signals decoded by are respectively supplied to the controlled objects. A portion of the control information read from the ROM 206 is input to the ROM address register 205 via the output buffer 204B. Decoder 2
A part of the control signal decoded at 14 is inputted to the output buffer 204A via the inverter 207 and directly to the output buffer 204B to control the opening and closing of these buffers. The data structure section 215 operates according to the control signal decoded by the decoder 214. For example, in the case of addition, data on the data bus 201 is stored in a buffer register 208 and connected to one of the arithmetic gates 209. Further, the summand is read from the register file 211 and added to the other side of the arithmetic gate 209. After adding these two inputs, the arithmetic circuit 209 stores it in the buffer register 210, and stores it in the storage target register in the register file 211, and ends the process. This processing result is also transferred from the register file 211 to the data bus 201 via the output buffer 204C.
will be sent as necessary. Status information at the time of the operation, such as positive, negative, even, odd overflow, occurrence of carry, etc. regarding the result of this operation is stored in the flag storage register 212. This status information is used as branch information of the microprogram, and in order to make a decision branch in the execution routine mentioned above, the contents to be decided are specified in the ROM 206.
After being set in the microinstruction register 220, it is decoded by the decoder 214 and input to the selection input terminal of the data selector 213. The status information of the flag storage register 212 is added as a data input to the data selector 213, and the contents selected by the selector terminal are transferred to the condition fulfillment signal line 217. The condition fulfillment signal line 217 is connected to the ROM address register 205 and is connected to the output buffer 204A or 204.
The control information added by B is stored in the register 205.
Specify whether to re-store the data or increment the currently stored content. As a result, branching is performed depending on the content of the condition fulfillment signal line 217. Therefore, when it is desired to branch based on the content of data on the data bus 201, this data is taken into the data structure unit 215, the status is set in the flag storage register 212, and the microprogram specifies the desired branch. , branches have to be made, especially when there are a number of decisions to be made, and when multiple branches are desired, a large number of microprogram steps are required, causing processing delays.

The present invention is to provide a multi-jump method that can perform a large number of branches at high speed.More specifically, it is an object of the present invention to provide a multi-jump method that can perform a large number of branches at high speed. At this point, by specifying it in the microprogram, part or all of the data on the device can be used as an element for multi-branching (in reality, a ROM address), and in the instruction execution routine. The feature is that multiple branches can be made to various processing subroutines in one go.

An embodiment of the present invention will be described with reference to FIG. In particular, the present invention is an improvement in the control structure. In addition, in Figure 3, to simplify the drawing,
Only the improved control structure is shown; the data structure shown in FIG. 2 is not shown. A jump data latch register 303 connected to the data bus 201 is provided in the control structure section. The jump data set signal generated by the specification from the microprogram on line 352 and the timing pulse on line 353 are sent to register 30 via AND gate 306A.
3 is input to the set terminal, and the data set is
It will be done. This timing pulse is generated by a control circuit (not shown) within the computer.

The output of the register 303 is sent to the data selector 304
is input to the microprogram address generator 203A through the microprogram address generator 203A. This microprogram address generator 203A creates the address of the microprogram to be executed next, and this circuit generally uses the input signal bit number and ROM
Since the number of address bits differs, it is used for signal modification such as bit length conversion, polarity change, and bit arrangement swapping, and is composed of PLA, ROM, or random gates. The other input of the data selector 304 is connected to the output of the instruction register 202 and is used for multi-branching to an instruction execution routine. Further, the output of the address generator 203A is input to the ROM address register 205 through an output buffer 204A. The output of this register 205 is added to the ROM 206 as address information. The output from ROM 206 is latched into microinstruction register 220, and the output is sent to decoder 214.
After being decoded, it is connected to each controlled object as a control signal. The bus multi-jump flag set signal on line 351 is ANDed with the timing pulse on line 353 to the set input terminal of bus multi-jump flag register 305 for executing bus multi-jump to perform multiple branches according to the contents of jump data latch register 303. gate 3
After being ANDed at 06B, it is input. In addition, this bus multi-jump flag register 30
The signal on line 350 and the timing pulse on line 353 are connected to the reset terminal of AND gate 3.
After being ANDed at 06C, it is input. The output of the flag register 305 is sent to the data selector 30.
It is input to the selection signal input terminal No. 4. When the flag register 305 is set, the contents of the jump data latch register 303 are input to the microprogram address generator 203A by the data selector 304, and when the flag register 305 is reset, the contents of the jump data latch register 303 are input to the microprogram address generator 203A. The contents of are inputted by the data selector 304. The output of the flag register 305 is input to this generator 203A, and when the flag register 305 is in the set state, it generates an address for the jump data in the register 303, and when the flag register 305 is in the reset state, it generates the address for the jump data in the register 303. An address for the instruction in the instruction register 202 is generated. By doing this, it becomes possible to set the contents of the data bus 201 in the ROM address register 205, and it becomes possible to perform multiple branches depending on the contents of the data on the data bus 201. The output buffers 204A and 204B are 3-state buffers or open collector output buffers, and are used when setting the jump destination address of the contents of the ROM 206 in the ROM address register 205.The output buffers 204A and 204B are always opposite. to work. That is, only one of 204A and 204B is open. That is, when output buffer 204A is opened by the decoded signal on line 350, address generator 203A
The output of is set in the ROM address register 205. Note that at this time, a signal obtained by inverting the signal on line 350 by inverter 312 is applied to output buffer 204B. Therefore, output buffer 204B is closed. Conversely, when the signal on line 350 causes output buffer 204A to close, output buffer 204B is open and therefore the signal on line 362 is set in ROM address register 205. These output buffers are used when it is necessary to jump, for example when branching or jumping when a multi-jump is not specified, since it is impossible to arrange a microprogram if the ROM address is always incremented (+1). That is, condition determination is performed based on status information selected from a flag storage register (not shown) in a data structure section (not shown), and line 2
17, the ROM address register 205 outputs the output buffer 204A, 2
When the output of 04B is taken in and the condition fulfillment signal is not output on the line 217, the ROM address register 205 stores the currently stored address as +
Store the address incremented by 1.
FIG. 4 shows an example of specifying a microprogram when performing multi-branching using the present invention. Figure 5 a, b,
4. c and d show the designation of the microprogram shown in FIG. 4, and the timing of setting and resetting the data latch register and multi-jump flag register. Hereinafter, the multi-jump operation according to FIG. 3 will be explained based on FIGS. 4 and 5. Note that FIG. 5a represents the designation of the microprogram to be executed at each time, and b represents the line 3.
53, and c and d indicate the set and reset states of the jump data latch register and multi-jump flag register, respectively. As shown in FIG. 5, microprogram specifications for multi-jump include set jump data specification 400, set bus multi-jump flag specification 402, and multi-jump specification 404.
It becomes more. As shown in FIG. 5a, at time _T11 , the set jump data designation 400 is
06 and set in the microinstruction register 220. As a result, decoder 214 outputs a signal on line 352 that sets jump data latch register 303. This latch register 303 is connected to the data bus 20
Set the jump data above 1. At time _T12 , the timing pulse on line 353 drops from a high level to a low level, as shown in FIG. 5b. As a result, the output of AND gate 306A drops from a high level to a low level. Jump data latch register 303 sets the signal on data bus 201 in response to a change in the output of AND gate 306A, as shown in FIG. 5c. Next, the set bus multi-jump flag designation is set in the microinstruction register 220 at time _T21 . As a result, decoder 214 outputs signals for two flag sets on line 351. At time T ₂₁ , the timing pulse on line 353 changes from low to high, but then changes from high to low again at time T ₃₁ . This change also appears in the output of AND gate 306B. Bus multi-jump flag register 305 enters the set state in response to this change. As a result, data selector 304 inputs the jump data latched in jump data latch register 303 to microprogram address generator 203A. As a result, this address generator 203A will generate a ROM address corresponding to the jump data. Thereafter, at time _T31 , the multijump designation is read into the microinstruction register. As a result, a multi-jump activation signal is output from decoder 214 on line 350. This signal causes output buffer 204A to open and output buffer 204B to close. As a result, ROM2
The address output from 06 is not input to the ROM address register, but the output of the microprogram address generator 203A is input to the ROM address register. This generator 203
From A, jump data latch register 303
For the jump data stored in
Since the ROM address is output, in the end,
The ROM address register 205 has data bus 2.
Regarding jump data sent from 01
The ROM address will be set. The bus multi-jump flag register 305 becomes unnecessary when the address data is set in the ROM address register 309, and when multi-branching to the instruction execution routine due to the contents (instructions) of the instruction register 202 in the case of the next instruction fetch. Since it is not possible to set up to
It is input to the reset terminal of this flag 305 via C, and is automatically reset at the falling edge of the timing pulse at time _T32 . In this way, one jump operation of the multi-jump is completed. By using this method, the flow of a microprogram based on conventional judgment and branching can be processed by the multiple branching performed in one shot by the present invention, and processing speed can be improved. The following describes an example of the processing when performing the following. As shown in FIG. 6, a computer instruction consists of an instruction section, a modification section that modifies an address, and an ADDR section.
Here, the instruction part is “READ”, “WRITE”, “ADD”
However, if the processing is insufficient with only this part, or if the instruction specifications are open to the user and can be expanded freely, a specific code is assigned to the instruction part and the actual processing content is at the effective address. It is assumed that the data is given in the form of "FUNCTION", and the CPU determines this and processes it. In this example, an example of the processing is shown in FIG. That is, the FUNCTION section instructs the operation of the protection function and timer function.

FIG. 8 shows this process realized using the conventional decision branching method, and only the instruction processing routine is shown. As you can see from the diagram, the contents of FUNCTION are stored in the accumulator in order to decode them.
In order to calculate and interpret the contents of FUNCTION one by one, starting the watchdog timer requires a long process flow of more than 10 steps 700 to 718, 8.
02 to 810 is required, making it unsuitable for computers that require high-speed processing. Figure 9 shows the processing flow when using the present invention.
is set in the jump data register, and a branch is made to the next microprogram address to be executed according to this content. (In the present invention, this is called multi-jump "multi-branching")
Therefore, as shown in the figure, any processing requires only four steps, which means that the number of processing steps can be greatly reduced, or the processing speed can be increased.
In addition, a feature of this method is that the value on the data bus
Since branching can be performed freely, the branch destination address of the microprogram can be stored in any register in the data structure section (not shown) (e.g., an accumulator, an accumulator extension, a work register, etc.) on the data bus. It can also be stored in a main memory such as a core memory, and the above registers and main memory can be freely used as a return register for a subroutine at the microprogram level.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the flow of conventional microprogram processing, FIG. 2 is a schematic diagram of the data structure section and control structure section of a conventional computer, and FIG. 3 is a diagram showing the control structure of the present invention. 4 shows an example of microprogram specification when using the bus multi-jump according to the present invention, and FIG. 5 a, b, c, and d show the specified timing and timing pulse of FIG. 4, respectively. Figure 6 shows an example of a computer instruction format; Figure 7 shows an example of processing specifications in the instruction extension;
The figure shows an example of a processing flow in a conventional example, and FIG. 9 shows an example of a processing flow according to the present invention. 303...Jump data latch register, 20
2... Instruction register, 304... Data selector, 203A... Micro program address generator, 305... Multi-jump flag register.

Claims (1)

[Claims] 1. A jump data latch register connected to a data bus and storing data for determining the address of a microprogram, an instruction register connected to the data bus, a storage device storing a microprogram, and a jump data latch register connected to the data bus. In response to the output of the register and the instruction register, a microprogram address generator for generating the storage device, and outputs of the jump data latch register and the instruction register are switched to generate the microprogram. A data selector for inputting to the address generator and a multi-jump flag register for instructing the microprogram to be executed based on the data in the jump data latch register are provided. The data selector switches and outputs the outputs of the jump data latch register and the instruction register according to the output of the multi-jump flag register. A bus multi-jump system characterized by the following configuration.