JPS5537645A - Microcomputer circuit - Google Patents

Microcomputer circuit

Info

Publication number
JPS5537645A
JPS5537645A JP11041978A JP11041978A JPS5537645A JP S5537645 A JPS5537645 A JP S5537645A JP 11041978 A JP11041978 A JP 11041978A JP 11041978 A JP11041978 A JP 11041978A JP S5537645 A JPS5537645 A JP S5537645A
Authority
JP
Japan
Prior art keywords
register
bank address
address
instruction
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11041978A
Other languages
Japanese (ja)
Other versions
JPS5719466B2 (en
Inventor
Yoshiaki Daimatsu
Takashi Sakao
Toshiaki Suzuki
Kazuaki Mayumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11041978A priority Critical patent/JPS5537645A/en
Publication of JPS5537645A publication Critical patent/JPS5537645A/en
Publication of JPS5719466B2 publication Critical patent/JPS5719466B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)

Abstract

PURPOSE: To simplify program development by increasing the address assignment of ROM by adding a bank address register to a one-chip microcomputer.
CONSTITUTION: One-chip microcomputer 14 is stored with programs in ROM12. Adding bank address register 13 to this constitutes appreciation chip 15. An instruction from ROM2 addressed by program counter 1 is fetched by instruction register 3 and then decoded by instruction decoder 4. By an input of band address set signal (4) or bank address reset signal (m) form decoder 4, auxiliary bank address register 13b and delay circuit 16 are operated and when output signal (o) of circuit 16 and address assignment signal (n) from decoder 4 are supplied, data from register 13b is received bu main bank address register 13a to store an assigned jump-destination address in ROM2. The entire area of ROM is used for user's programs and program development is simplified.
COPYRIGHT: (C)1980,JPO&Japio
JP11041978A 1978-09-07 1978-09-07 Microcomputer circuit Granted JPS5537645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11041978A JPS5537645A (en) 1978-09-07 1978-09-07 Microcomputer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11041978A JPS5537645A (en) 1978-09-07 1978-09-07 Microcomputer circuit

Publications (2)

Publication Number Publication Date
JPS5537645A true JPS5537645A (en) 1980-03-15
JPS5719466B2 JPS5719466B2 (en) 1982-04-22

Family

ID=14535278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11041978A Granted JPS5537645A (en) 1978-09-07 1978-09-07 Microcomputer circuit

Country Status (1)

Country Link
JP (1) JPS5537645A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0198302U (en) * 1987-12-21 1989-06-30

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0198302U (en) * 1987-12-21 1989-06-30

Also Published As

Publication number Publication date
JPS5719466B2 (en) 1982-04-22

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