JPS5538603A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To simplify greatly a peripheral timing unit by connecting holding circuits for an address input, data input and data output of a memory element array, and by providing a delay method for a clock signal. CONSTITUTION:On an arrival of clock signal 120 of ''1'', common holding timing signal 125 is generated with time delay of delay circuit 111 and timing signal 126 is also generated by delay circuit 112 with further time delay. Input data 121, address input 123 and write signal 124 are held by holding circuits 106-108 at a point in time of a rise of signal 125. Write control signal generating circuit 110, on the other hand, is reset in a rise of signal 120 and set in a rise of signal 126 to generate output 127. At the output of AND circuit 113, write control signal of memory element array 101 appears. Here, signal 105 is inputted being delayed by a difference in delay time between circuits 112 and 111 by input data 103 and address input signal 102. Further, signal 105 falls leading by the delay time of circuit 11 before a point in time when inputs 103 and 102 changes at next time.