JPS578979A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS578979A
JPS578979A JP8235480A JP8235480A JPS578979A JP S578979 A JPS578979 A JP S578979A JP 8235480 A JP8235480 A JP 8235480A JP 8235480 A JP8235480 A JP 8235480A JP S578979 A JPS578979 A JP S578979A
Authority
JP
Japan
Prior art keywords
circuit
signal
output signal
inputted
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8235480A
Other languages
Japanese (ja)
Inventor
Hiroshi Miyajima
Isato Kazama
Kenji Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8235480A priority Critical patent/JPS578979A/en
Publication of JPS578979A publication Critical patent/JPS578979A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To control an integrated circuit by selecting an expected address accurately by activating a passive internal control signal while an address input signal is being inputted, and then by passivating it. CONSTITUTION:An address decoder 2 outputs a control signal (CS) 4. This CS signal 4 is inputted to a buffer circuit 5 and an inverter circuit 6 in an internal control signal generating circuit 13. The output signal of this buffer circuit 5 is inputted to a delay circuit 7, which outputs an output signal 8 delayed by a delay time D1. The output signal of the inverter circuit 6, on the other hand, is inputted to a dalay circuit 9, whose output signal 10 rises a dealy time D2 later. Therefore, an AND circuit 11 ANDs the output signal and output signal 10 to output an internal CS signal 12.
JP8235480A 1980-06-17 1980-06-17 Integrated circuit Pending JPS578979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8235480A JPS578979A (en) 1980-06-17 1980-06-17 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8235480A JPS578979A (en) 1980-06-17 1980-06-17 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS578979A true JPS578979A (en) 1982-01-18

Family

ID=13772231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8235480A Pending JPS578979A (en) 1980-06-17 1980-06-17 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS578979A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5963094A (en) * 1982-10-04 1984-04-10 Fujitsu Ltd Memory device
JPS6238593A (en) * 1985-08-14 1987-02-19 Fujitsu Ltd Dynamic semiconductor storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5963094A (en) * 1982-10-04 1984-04-10 Fujitsu Ltd Memory device
JPS6238593A (en) * 1985-08-14 1987-02-19 Fujitsu Ltd Dynamic semiconductor storage device

Similar Documents

Publication Publication Date Title
JPS5787620A (en) Clock generating circuit
JPS5538603A (en) Semiconductor memory device
JPS578979A (en) Integrated circuit
JPS5632824A (en) Pulse eliminating circuit
JPS5538604A (en) Memory device
JPS57179979A (en) Clock signal generating circuit
JPS5528542A (en) Clock generation system
JPS57112129A (en) Latch circuit
JPS57198593A (en) Memory circuit
JPS5559579A (en) Sequence controller
JPS57191753A (en) Register controlling system
JPS5587201A (en) Double system controller
JPS5545221A (en) Clock break detection circuit
JPS6453396A (en) Output buffer circuit
JPS5329480A (en) Program controller
JPS6416013A (en) Clock distribution circuit
JPS56123779A (en) Method for gate turn-off for thyristor inverter
JPS56140600A (en) Reader for read-only memory
JPS5718147A (en) Synchronizer
JPS57188140A (en) Reference signal generating circuit
JPS5771054A (en) Microprogram controller
JPS56159723A (en) Clock switching control system
JPS56154820A (en) Pulse shaping circuit
JPS6424510A (en) Preventing circuit for malfunction of up/down counter
JPS5429953A (en) Frequency multiplier circuit