JPS5543636A - Digital device - Google Patents

Digital device

Info

Publication number
JPS5543636A
JPS5543636A JP11592878A JP11592878A JPS5543636A JP S5543636 A JPS5543636 A JP S5543636A JP 11592878 A JP11592878 A JP 11592878A JP 11592878 A JP11592878 A JP 11592878A JP S5543636 A JPS5543636 A JP S5543636A
Authority
JP
Japan
Prior art keywords
bus
data
signal
control
allotment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11592878A
Other languages
Japanese (ja)
Other versions
JPS6042974B2 (en
Inventor
Masahiro Iwamura
Nagaharu Hamada
Fumiya Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11592878A priority Critical patent/JPS6042974B2/en
Publication of JPS5543636A publication Critical patent/JPS5543636A/en
Publication of JPS6042974B2 publication Critical patent/JPS6042974B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To obtain various control functions by installing the signal allotment circuit within the digital device to secure an optional allotment for the input/output end about the control signal to which control function is relating.
CONSTITUTION: Control function modules C1WCn incorporating digital device 2000 are controlled by internal control signals Y1WYn to deliver output U1WUn. Processor 500 provided at the outside is connected to signal allotment circuits 10 and 20 via data bus DB and address bus AB, and processor 500 gives the control so that the data of bus DB may be written into the address designated by bus AB. Within circuits 10 and 20, the assignment register is provided to memorize the data of bus DB along with the decoder which decodes the contents of bus AB and delivers the writing signal to make the assignment register corresponding to the contents write the data of bus DB.
COPYRIGHT: (C)1980,JPO&Japio
JP11592878A 1978-09-22 1978-09-22 digital equipment Expired JPS6042974B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11592878A JPS6042974B2 (en) 1978-09-22 1978-09-22 digital equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11592878A JPS6042974B2 (en) 1978-09-22 1978-09-22 digital equipment

Publications (2)

Publication Number Publication Date
JPS5543636A true JPS5543636A (en) 1980-03-27
JPS6042974B2 JPS6042974B2 (en) 1985-09-26

Family

ID=14674653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11592878A Expired JPS6042974B2 (en) 1978-09-22 1978-09-22 digital equipment

Country Status (1)

Country Link
JP (1) JPS6042974B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60241762A (en) * 1984-05-15 1985-11-30 Mabuchi Motor Co Ltd Small-sized motor
JPH04232554A (en) * 1990-05-18 1992-08-20 Internatl Business Mach Corp <Ibm> I/o control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60241762A (en) * 1984-05-15 1985-11-30 Mabuchi Motor Co Ltd Small-sized motor
JPH04232554A (en) * 1990-05-18 1992-08-20 Internatl Business Mach Corp <Ibm> I/o control system

Also Published As

Publication number Publication date
JPS6042974B2 (en) 1985-09-26

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