JPS6042974B2 - digital equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital device that performs a desired operation by inputting a digital signal, and particularly relates to an improvement of a digital device that has a limited number of terminals for inputting or outputting digital signals.

In digital devices that input and output digital signals,
A digital signal (hereinafter referred to as a control signal) for controlling each functional module that performs each operation within the device.

) input or output. On the other hand, digital devices are required to include more functions and are also required to be more compact. In response to such demands, digital devices are being integrated and configured on one semiconductor chip. In such integration, it is important to increase the internal functions of the semiconductor chip as much as possible and make it as versatile as possible.However, the problem here is that if the internal functions are increased, , the number of input/output pins increases in proportion to the number of functions.Increasing the number of input/output pins means increasing the number of pins on the package, and as a result, the number of pins on the package is limited. This creates an unreasonable situation where the number of built-in functions is limited.The easiest way to solve this problem is to prepare a package with a larger number of pins, but as integration progresses, special packages will be prepared to accommodate this. However, when considering technical and cost aspects, there are naturally limitations and it is not realistic.
Therefore, in the past, the number of pins of the package in which the semiconductor chip was assembled often became a bottleneck, and some of the control functions could not be included.

The present invention was made in view of the above-mentioned problems.
It is an object of the present invention to provide a digital device in which more control function modules can be assigned to a limited number of input/output signals than the number of input/output signals provided in the digital device. According to the digital device of the present invention, it is possible to arbitrarily allocate a control signal related to which control function the input/output terminal corresponds to a part or all of the input/output terminal for inputting/outputting a signal. A signal allocation circuit is provided within the digital device, and the output of the signal allocation circuit is configured to be a control signal for each control function.

Objects and features of the present invention other than those described above will become clear from the following description.

Hereinafter, the present invention will be explained with reference to drawings of specific embodiments.

FIG. 1 shows the configuration of a conventional digital device.

1000 is a digital device, in this example C
It has four control functions, 1 to C4. 11-14 are input ends, and 01-04 are output ends.

Input signals X1 to X4 for operating each control function of Cl9C4 are input from this input terminal. Outputs Z1 to Z4 of each control function are output from output terminals 01 to 04. In this method, when the digital device 1000 is integrated on a semiconductor chip, the more control functions it has, the more
The number of input terminals and output terminals increases, and when these are incorporated into a package, the number of built-in control functions is limited by the limited number of pins. In other words, it ends up being less versatile. FIG. 2 is a block diagram showing the basic configuration of the present invention. According to this configuration, the limitation on the number of pins does not affect the number of control functions.

In Figure 2, X1 to \ are input signals, Z1 to B are output signals, 10 and 20 are signal allocation circuits on the input side and output side, and 5
00 is an information generating device that outputs information for signal allocation to a signal allocation circuit, and in this example is a microprocessor. C1 to Cn are control function modules built into the digital device 2000. Y1 to Yn are internal control signals for operating each control function module C1 to Cn. Microprocessor 500 may be built into digital device 2000, but in this example it is provided outside device 2000. The processor 500 and the signal allocation circuits 10 and 20 are connected by a data bus DB and an address bus AB.
0 controls data on the data bus DB to be written to the address specified on the address bus AB. The signal assignment circuits 16 and 20 include a register (hereinafter referred to as an assignment register) for storing data of DB, which is an assignment setting means, and a register that decodes the contents of AB and stores the data in an assignment register corresponding to the contents. It includes a decoder that outputs a write signal for writing data in the DB. Signal allocation circuit on the input side (corresponds to 10 in FIG. 2).

) is shown in FIG. 3. In Figure 3, 1
01 is an address decoder that decodes the contents of the address bus AB and outputs a write signal. 111, 112, 11
Reference numerals 3 and 114 indicate assignment registers provided corresponding to the signals X1 to X4 inputted from each input terminal, and the assignment data carried on the data bus DB is stored in these registers according to the write signal from the decoder. be remembered.

In other words, the contents stored in the assignment register are for determining which of the control signals Y1 to Y8 each input signal X1 to X4 corresponds to. 121, 122, 123
, 124 is a distribution circuit that determines whether the input signals X1, X2, X3, \ are to be used as control signals for operating the control function that matches the contents of the assign register.

Reference numeral 102 is a collective circuit that collects the outputs of each distribution circuit and outputs a control signal that also operates each control function.

In this example, the collective circuit 102 is connected to the distribution circuits 121 to 124.
All the signals output to the output signal lines 105 to 108 are inputted, but the configuration is not necessarily like this. This will become clear from the description of other embodiments to be described later. Now, in FIG. 3, consider the case where it is desired to use the input signal X1, which is now applied to the 11th terminal, as the control signal Y2.

In this case, the processor 500 outputs data indicating that the 11th end is Y2 to DB, and outputs an address signal indicating the assignment register 111 to AB. As a result, the decoder 101 outputs a write signal to the assign register 111, and the data output (loaded) to the DB is written to the assign register 111. The distribution circuit 121 that takes in the contents of the assignment register 111 is
Distribute so that 1 becomes Y2. This distribution circuit 121 is specifically composed of AND gates corresponding to Y1 to Y8, and one input terminal of the AND gate is provided with an assignment register 1.
The contents of each bit of 11 are input, and X1 is commonly input to the other input terminals of all AND gates. Therefore, the contents of the assign register 111 are limited to the bit 66r2 corresponding to the input terminal of the AND gate A2 corresponding to Y2.
If so, it can be seen that X1 is valid only as the output of the AND gate A2. In this way, the distribution circuit can output an internal control signal according to the contents of the assignment register. The control signal output to the signal line 105 is output to the collective circuit 102, and the Y2 control signal is output. Third
A more specific circuit of the distribution circuit and collective circuit in the figure is shown in FIG.

In FIG. 4, 121 and 124 are the distribution circuits in FIG. 3, and 122 and 123 are omitted in this figure. 102 indicates a collective circuit.

Decoders 130 and 140 decode the contents of the assignment registers 111 and 114 and output a signal to one of the AND gates (hereinafter referred to as assignment decoders).

). 131 to 138 are AND gates provided corresponding to the controls Y1 to Y8 corresponding to the eight control functions, and 141 to 148 are also similar AND gates.

The input terminals of the OR gates 151 to 158 constituting the attack circuit 102 receive the output of the corresponding AND gate from the AND gate group of each distribution circuit. That is, the respective outputs of the AND gates 131 to 138 provided corresponding to Y1 to Y8 of the distribution circuit 121 are sent to the collective circuit 1.
OR circuit 151 provided corresponding to Y1 to Y8 of 02
~158 respectively corresponding inputs. OR circuit 1
The outputs of the corresponding AND gates of the other distribution circuits are given to the other input terminals 51 to 158. For example, an AND gate 141 provided corresponding to Y1 of the distribution circuit 124
The output becomes one input of the OR gate 151 provided corresponding to Y1 of the collective circuit 102. The same applies to others. The number of input terminals of the OR gate is the input signal X1 to X
It corresponds to 4. The reason why the distribution circuit and the collective circuit have such a configuration is to enable each of the input signals X1 to X4 to become any of the internal control signals Y1 to Y8. The operation shown in FIG. 4 will be explained.

Now, as described above, if it is desired to use the signal X1 applied to the input terminal 11 as the control signal Y2, the procedure is as follows. Assign register 111 has data bus DB.
The signal ゜゜00F゛ is stored. As a result, the assign decoder 130 decodes "゜00F" and outputs an activation signal to the No. 1 signal line. As a result, the signal X1 is output from the AND gate 132, and further output from the OR gate 152 to control If the signal X1 input from 11 is to be used as another control signal, the contents of the assign register 111 may be rewritten.

For example, if you want to use the signal X1 given to 11 as Y8, change the contents of the assign register 111 to
This can be achieved by setting it to 11゛. That is, since the content of the assignment register 111 is ゜゜11F゛, the assignment decoder 130 outputs an energizing signal from the signal line 7.
As a result, the signal X1 becomes the output of the AND gate 138, and is output from the OR gate 158 to become the control signal Y8. Of course, the signal X4 input from the terminal 11 can be any of the control signals Y1 to Y8. For example, if X4 becomes X7, assign register 11
All you have to do is write 46110゛ in 4. In other words, this ゜4
11', the assignment decoder 140 outputs an AND gate activation signal from the signal line 6. As a result, X4 becomes the output of the AND gate 147, becomes the output of the OR gate 157 to which it is input, and becomes the control signal Y7.
In the above example, an assignment decoder was provided in the distribution circuit, but it is also possible to configure the assignment register with bits equal to the number of control signals and apply the output of each assignment register to one input terminal of the AND gate. .

FIG. 5 shows such a configuration. FIG. 5 shows one distribution circuit and one assignment register in detail. The assignment register 11 is composed of the same number of bits as the number of control signals, and the output thereof is inputted to one input terminal of AND gate groups 131 to 138 forming the distribution circuit 121, respectively. What is different from the distribution circuit and assignment registers (for example, 111, 121) shown in FIG. 4 is that the one in FIG. Therefore, the number of register bits has increased. Next, there is a signal allocation circuit on the output side (corresponding to 20 in FIG. 2).

) is shown in FIG. 6. Essentially, the configuration is similar to that of the input side signal allocation circuit shown in FIG. In FIG. 6, 211 to 214 are assign registers in which data for selecting one of the outputs U1 to U8 from each control function is stored. 221 to 224 are distribution circuits.

A decoder 201 decodes the contents of the address bus and outputs a write signal for writing the data output to the data bus into one of the assign registers.

202 is a collective circuit, which in this case is composed of four OR gates 251 to 254 corresponding to four output terminals.

The operation of the signal allocation circuit shown in FIG. 6 is as follows. Now, for example, when outputting the internal output signal U1 from the output terminal 01 as the output signal B, the assignment register 211
Stores data for linking U1 and 01. As a result, the distribution circuit 221 guides U1 to the OR gate 251 in the collective circuit 202, and U1 is taken out from the output terminal 01 as an output signal B. According to such a configuration, by writing the contents of the assign register, it is possible to take out the internal control signals U1 to U8 from any of the output terminals 01 to 04. The distribution circuit 221 shown in FIG. 6 has a concrete configuration as shown in FIG. 7. The other distribution circuits 222 to 224 have similar configurations. In FIG. 7, 230 is the assignment register 2
This is an assignment decoder that receives the output of 11 and decodes its contents. 231-238 are AND gates provided corresponding to U1-U8.

Next, other embodiments of the input-side distribution circuit 10 and the output-side distribution circuit 20 in FIG. 2 will be described.

FIG. 8 shows an embodiment of the distribution circuit 10 on the input side.

In FIG. 8, the same numbers as in FIG. 3 indicate similar components. The major difference between FIG. 3 and FIG. 8 is that the aggregate circuit is removed from the signal allocation circuit 10. In the case of Fig. 3, the signals X1 to X4 applied to the input terminal
can be any of the control signals Y1 to Y8. In the case of FIG. 8, each input signal can only be a control signal for operating a predetermined control function. However, it can be used as any one of the plurality of predetermined control signals. For example, input end 1
According to the contents stored in the assignment register 112, one of the AND gates in the distribution circuit 122 is selected for the signal X2 added to the signal X2, and one of the control signals Y5 to Y8 is selected.
It becomes one. Therefore, X2 can be any of Y5 to Y8. However, X2 may be any of Y1 to Y4, or Y) to Yl. It is impossible to become either of these. Although there are some limitations in this respect, the intended purpose of eliminating limitations on internal control functions due to insufficient pin count of the package can be achieved. In a case like the example shown in FIG. 8, the items selected for the same group need to be such that there is no possibility of them being used at the same time. For example, X1 can be used as one control signal among the group of Y1 to Y4, but cannot be used as two control signals at the same time. If data is written to the assignment register 20 to use X1 as the control signal Y1,
X1 can only be used as Y1. Y1, Y5 and Y9
If Yl3 and Yl3 are used at the same time, there is no problem since they are provided by distribution circuits indicated by separate assign registers. Next, still another embodiment of the signal allocation circuit on the input side will be described. Figure 9 shows
It is a drawing which shows another Example. A feature of this embodiment is that it combines the embodiments shown in FIGS. 3 and 8 described above. That is, for the terminals 11 and 12, for example, 11
The configuration is such that the input X1 applied to can be a control signal for the group Y1 to Y4, but cannot be a control signal for the group Y5 to Y8. This is similar to the case of the embodiment of FIG. As for the terminals 13 and 14, the respective input signals are Y9 to Yl. This part is configured so that it can be any of the above.
Perform the same operation as shown in the figure. In this figure, 409 to 412 represent a collective circuit 100 of terminals 13 and 14.
It is an or gate that consists of. The configuration shown in Figure 9 is
It is practical in that the circuit is relatively simple and there is a degree of freedom in its use. Next, another embodiment of the signal allocation circuit 20 on the output side will be described.

On the output side, a configuration similar to that of the input side layout circuit shown in FIGS. 8 and 9 can be realized. That is, if the signal allocation circuit on the output side is configured based on the same idea as the embodiment shown in FIG. 8, it will be as shown in FIG. 10. In Figure 10, 201
is an address decoder, 211 and 212 are assignment registers, and 221 and 222 are distribution circuits. Distribution circuit 221
is the assignment decoder 230 and the AND gates 231 to 2.
Consists of 34. The distribution circuit 222 includes an assignment decoder 240 and AND gates 241 to 244.
This embodiment differs from the signal allocation circuit of FIG. 6 described above in that the collective circuit 202 is omitted. It should be noted that on the output side as well, it is possible to have a configuration that is a partial combination of FIGS. 6 and 10, similar to the input side signal allocation circuit shown in FIG.

As is clear from the above explanation, in the present invention, an input signal can be assigned as a desired internal control signal, or an internal output signal can be assigned as a desired external output signal, so that the internal control function can be The number is less affected by the number of input/output pins, making it possible to increase versatility. The following methods are available for writing the contents of the assign register provided for each input terminal using an information generating device (for example, a microprocessor). One method is to initialize it at system startup.

That is, at the time of use, the internal control function is selected by writing the contents of the assign register by some means. In this case, although it is possible to arbitrarily select the signal before use, it is not possible to freely change the signal input to the terminal during use, and the control signal must be a preselected control signal. Another method is to dynamically write the contents of the assign register while the system is operating.
With this method, a signal applied to one input terminal can be used as a control signal for operating an arbitrary control function. In the embodiments shown in FIGS. 3, 6, 8, 9, and 10 described above, it is possible to dynamically write the contents of the assign register during system operation. That is, in the above-described embodiment, the processor and the signal allocation circuit are connected, and the contents of the assignment register in the signal allocation circuit can be written at any time according to instructions from the processor. These two methods should be used depending on the particularity of the system in which the digital device of the present invention is used. Next, an example will be shown in which the present invention is applied to attribute control of a CRT display device.

As is well known, in a CRT display device, color control, brightness control, blinking control, reverse display control, and many other attributes are assigned to each displayed character or each field. However, each display device does not require all of the above-mentioned attributes, and as shown in FIG. 11, attributes of the model are given. Therefore, when converting the control part of the above attributes into an LSI as a general-purpose controller, there is almost no need to control all the attributes that can actually exist at the same time, and the control circuit inside the LSI can control all the attributes. A full menu for control is prepared as shown in B, and the menu can be selected for each individual display system.
For example, the number of pins of the LSI can be limited to a practical number by selecting as shown in A in FIG. FIG. 12 shows an example of application of the signal allocation circuit 10 to a CRT display device.

600 is a refresh memory that stores display data for one screen, and the character code portion of its output is sent to a character generator 61.
0 is converted to a dot pattern, and the shift register 620
is converted to a serial signal by AND gates 630-63
Connected to one input of 2.

In this embodiment, attributes X1 to X4 are assigned to each character, and the control details are as shown in A of FIG.
It looks like this. On the other hand, the attribute control circuit 2000 surrounded by the dotted line in FIG. 12 has eight types of attribute control functions shown in B in FIG. 7, and four of these are selected by the signal allocation circuit 10 on the input side. . That is, the attribute signals Xl, X2, X3 are assigned to the internal control signals Yl, Y2, Y3 and connected to other input terminals of the corresponding AND gates 630, 631, 632. As a result, color control is imparted to the video signal from the shift register 620, and the video amplifiers 640, 64
Color characters are displayed on the CRT display 700 through 1,642. Further, the attribute signal X4 is assigned to the internal control signal Y8 and the video amplifiers 640, 641,
By controlling the amplification degree of 642, the brightness of the displayed characters is controlled. As is clear from the above explanation, the present invention is applicable to LS where there is a realistic limit on the number of pins of the package and it is necessary to incorporate as many functions as possible internally for general purpose.
The effect is particularly noticeable when applied to I logic devices.

[Brief explanation of the drawing]

Figure 1 is a diagram for explaining a general digital device.
Fig. 2 shows an embodiment of the present invention, Fig. 3 shows a part of Fig. 2 (signal allocation circuit on the input side) in more detail, and Fig. 4 shows Fig. 3 in more detail. 5 is a diagram showing a modification of the configuration of a part of FIG. 4, FIG. 6 is a diagram showing a part of FIG. 2 (signal allocation circuit on the output side) in more detail, and FIG. The figure shows a part of the configuration of FIG. 6 in more detail, FIGS. 8 and 9 show another embodiment of the input side signal allocation circuit shown in FIG. 3, and FIG. FIG. 6 is a diagram showing another embodiment of the signal allocation circuit on the output side, FIG. 11 is a diagram showing an example of the control function of a display device, and FIG. 12 is a diagram showing an example of application of the present invention. be. DESCRIPTION OF SYMBOLS 10... Signal allocation circuit on the input side, 20... Signal allocation circuit on the output side, 500... Microprocessor, 1
01... Address decoder, 111-114... Assign register, 121-124... Distribution circuit, 10
2... Collective circuit, 201... Address decoder, 2
11-214...Assign register, 221-224
...Distribution circuit, 202...Collection circuit.

Claims (1)

[Claims] 1 A first assignment that has a plurality of control function modules inside and assigns which module among the plurality of control function modules each digital signal input from a plurality of input terminals is a signal for controlling. at least one of a second signal allocation circuit that allocates each internal output signal outputted from the plurality of control function modules to which output terminal among the plurality of output terminals the output signal is outputted as an output signal; In a digital device having a signal assignment circuit provided therein, the plurality of control function modules are provided in a number greater than the number of input side or output terminals, and assignment is set within the first and second signal assignment circuits. 1. A digital device comprising means for arbitrarily allocating the plurality of control function modules to signals for the input or output terminals based on allocation data set in the allocation setting means.