JPS5543862A - Semiconductor nonvolatile memory - Google Patents

Semiconductor nonvolatile memory

Info

Publication number
JPS5543862A
JPS5543862A JP11655078A JP11655078A JPS5543862A JP S5543862 A JPS5543862 A JP S5543862A JP 11655078 A JP11655078 A JP 11655078A JP 11655078 A JP11655078 A JP 11655078A JP S5543862 A JPS5543862 A JP S5543862A
Authority
JP
Japan
Prior art keywords
gate layer
drain
source
junction
nonvolatile memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11655078A
Other languages
Japanese (ja)
Inventor
Kazuhiro Komori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11655078A priority Critical patent/JPS5543862A/en
Publication of JPS5543862A publication Critical patent/JPS5543862A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/68Floating-gate IGFETs
    • H10D30/681Floating-gate IGFETs having only two programming levels

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To carry out information write to a gate layer at a drain junction and also to carry out information erase from the gate layer at a source junction by providing an adjacency to the channel area of a control gate layer nearly intermediately between source and drain. CONSTITUTION:A floating gate layer 16 is provided over a channel area 11 with an aperture 16A given on its center, and a part 28A of a control gate layer 28 is arranged so as to come in the aperture 16A. There is arranged a switching FETQs nearly intermediately between source and drain, which is equivalent to the case where a floating FETQf is arranged on both sides thereof. Thus information write can be carried out at the drain junction and information erase can also be carried out at the source junction.
JP11655078A 1978-09-25 1978-09-25 Semiconductor nonvolatile memory Pending JPS5543862A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11655078A JPS5543862A (en) 1978-09-25 1978-09-25 Semiconductor nonvolatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11655078A JPS5543862A (en) 1978-09-25 1978-09-25 Semiconductor nonvolatile memory

Publications (1)

Publication Number Publication Date
JPS5543862A true JPS5543862A (en) 1980-03-27

Family

ID=14689883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11655078A Pending JPS5543862A (en) 1978-09-25 1978-09-25 Semiconductor nonvolatile memory

Country Status (1)

Country Link
JP (1) JPS5543862A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0045578A3 (en) * 1980-07-28 1983-10-26 Fujitsu Limited Semiconductor memory device
US4596938A (en) * 1982-09-30 1986-06-24 Rca Corporation Electrically erasable programmable electronic circuits using programmable-threshold-voltage FET pairs
US5412600A (en) * 1991-10-09 1995-05-02 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor device with selecting transistor formed between adjacent memory transistors
US6091633A (en) * 1999-08-09 2000-07-18 Sandisk Corporation Memory array architecture utilizing global bit lines shared by multiple cells
US6103573A (en) * 1999-06-30 2000-08-15 Sandisk Corporation Processing techniques for making a dual floating gate EEPROM cell array
US6151248A (en) * 1999-06-30 2000-11-21 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
US6512263B1 (en) 2000-09-22 2003-01-28 Sandisk Corporation Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177184A (en) * 1974-12-27 1976-07-03 Sanyo Electric Co FUROOTEINGUGEETOKOZOOMOTSU HANDOTAI MEMORISOSHI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177184A (en) * 1974-12-27 1976-07-03 Sanyo Electric Co FUROOTEINGUGEETOKOZOOMOTSU HANDOTAI MEMORISOSHI

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0045578A3 (en) * 1980-07-28 1983-10-26 Fujitsu Limited Semiconductor memory device
US4596938A (en) * 1982-09-30 1986-06-24 Rca Corporation Electrically erasable programmable electronic circuits using programmable-threshold-voltage FET pairs
US5412600A (en) * 1991-10-09 1995-05-02 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor device with selecting transistor formed between adjacent memory transistors
US6420231B1 (en) 1999-06-30 2002-07-16 Sandisk Corporation Processing techniques for making a dual floating gate EEPROM cell array
US6103573A (en) * 1999-06-30 2000-08-15 Sandisk Corporation Processing techniques for making a dual floating gate EEPROM cell array
US6151248A (en) * 1999-06-30 2000-11-21 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
US6266278B1 (en) 1999-06-30 2001-07-24 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared adjacent cells
US6344993B1 (en) 1999-06-30 2002-02-05 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
US6091633A (en) * 1999-08-09 2000-07-18 Sandisk Corporation Memory array architecture utilizing global bit lines shared by multiple cells
US6512263B1 (en) 2000-09-22 2003-01-28 Sandisk Corporation Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming
US6723604B2 (en) 2000-09-22 2004-04-20 Sandisk Corporation Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming
US6953964B2 (en) 2000-09-22 2005-10-11 Sandisk Corporation Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming
US7288455B2 (en) 2000-09-22 2007-10-30 Sandisk Corporation Method of forming non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors
US7541237B2 (en) 2000-09-22 2009-06-02 Sandisk Corporation Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming

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