JPS5544737A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS5544737A
JPS5544737A JP11817278A JP11817278A JPS5544737A JP S5544737 A JPS5544737 A JP S5544737A JP 11817278 A JP11817278 A JP 11817278A JP 11817278 A JP11817278 A JP 11817278A JP S5544737 A JPS5544737 A JP S5544737A
Authority
JP
Japan
Prior art keywords
resin
substrate
conductor layer
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11817278A
Other languages
Japanese (ja)
Inventor
Tetsuo Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11817278A priority Critical patent/JPS5544737A/en
Publication of JPS5544737A publication Critical patent/JPS5544737A/en
Pending legal-status Critical Current

Links

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: To stably operate this device under a condition that outside circuits do not interfere, by coating this device with insulating resin, and by covering a surface of the insulating resin with conductive resin.
CONSTITUTION: An insulating substrate 4 provided with a back conductor layer 2 and a surface conductor layer 3 is melting sticked on a conductor substrate 1 in metal. A circuit element 5 of a transistor, a condenser, a coil, etc. is installed onto the conductor layer 3 on the substrate 4, and this hybrid integrated circuit device formed is coated with insulating resin 6. The whole surface of the resin 6 on a surface of this device is covered with conductive resin 7, and internal parts, etc. are shielded by the resin 7 in the substrate 1, thus ensuring action that is not interfered by means of outside circuits and is stable.
COPYRIGHT: (C)1980,JPO&Japio
JP11817278A 1978-09-25 1978-09-25 Hybrid integrated circuit device Pending JPS5544737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11817278A JPS5544737A (en) 1978-09-25 1978-09-25 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11817278A JPS5544737A (en) 1978-09-25 1978-09-25 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5544737A true JPS5544737A (en) 1980-03-29

Family

ID=14729895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11817278A Pending JPS5544737A (en) 1978-09-25 1978-09-25 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5544737A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59158333U (en) * 1983-04-11 1984-10-24 東光株式会社 Hybrid integrated circuit device
US5278580A (en) * 1991-02-06 1994-01-11 Rohm Co., Ltd. Thermal head
US9929078B2 (en) 2016-01-14 2018-03-27 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59158333U (en) * 1983-04-11 1984-10-24 東光株式会社 Hybrid integrated circuit device
US5278580A (en) * 1991-02-06 1994-01-11 Rohm Co., Ltd. Thermal head
US9929078B2 (en) 2016-01-14 2018-03-27 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

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