JPS554682A - Addressing digital input device - Google Patents

Addressing digital input device

Info

Publication number
JPS554682A
JPS554682A JP7835278A JP7835278A JPS554682A JP S554682 A JPS554682 A JP S554682A JP 7835278 A JP7835278 A JP 7835278A JP 7835278 A JP7835278 A JP 7835278A JP S554682 A JPS554682 A JP S554682A
Authority
JP
Japan
Prior art keywords
circuit
output level
fault
detection circuit
channels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7835278A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Saito
Kikuo Kogure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7835278A priority Critical patent/JPS554682A/en
Publication of JPS554682A publication Critical patent/JPS554682A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To prevent the malfunction for the input device by detecting the output level of the channel selection circuit via the output level detection circuit, deciding the normality of the detection value through the fault detection circuit and thus detecting quickly the fault for the plural number of the channels.
CONSTITUTION: Channel control circuit 15 delivers the channel selection signals so that a number of digital data of the process are read in sequentially and every fixed time, and the input channels are set up in sequence by channel selection circuit CH. And the digital data selected by circuit CH and read in are memorized in memory device 11, and then read out to be sent to the external unit. Here output level detection circuit 12 detects the output level of circuit CH and monitors the operation of the output level, and the normality is decided by fault detection circuit 13 and based on the detection value of circuit 12. And in case some fault is detected, the alarm signal is delivered. As a result, the faults such as the simultaneous selection, the nonselection of plural channels and others can be detected quickly, thus preventing the malfunction.
COPYRIGHT: (C)1980,JPO&Japio
JP7835278A 1978-06-28 1978-06-28 Addressing digital input device Pending JPS554682A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7835278A JPS554682A (en) 1978-06-28 1978-06-28 Addressing digital input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7835278A JPS554682A (en) 1978-06-28 1978-06-28 Addressing digital input device

Publications (1)

Publication Number Publication Date
JPS554682A true JPS554682A (en) 1980-01-14

Family

ID=13659585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7835278A Pending JPS554682A (en) 1978-06-28 1978-06-28 Addressing digital input device

Country Status (1)

Country Link
JP (1) JPS554682A (en)

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