JPS5552155A - Check system of arithmetic logical operation unit - Google Patents

Check system of arithmetic logical operation unit

Info

Publication number
JPS5552155A
JPS5552155A JP12414778A JP12414778A JPS5552155A JP S5552155 A JPS5552155 A JP S5552155A JP 12414778 A JP12414778 A JP 12414778A JP 12414778 A JP12414778 A JP 12414778A JP S5552155 A JPS5552155 A JP S5552155A
Authority
JP
Japan
Prior art keywords
operation unit
logical operation
arithmetic logical
output
transfer instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12414778A
Other languages
Japanese (ja)
Inventor
Kiyoutarou Imaizumi
Takashi Oka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12414778A priority Critical patent/JPS5552155A/en
Publication of JPS5552155A publication Critical patent/JPS5552155A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To perform error check of the arithmetic logical operation unit with a simple circuit, by comparing the specific input of the arithmetic logical operation unit and the output to it at the execution of transfer instruction.
CONSTITUTION: The input a and the output d of the arithmetic logical operation unit 11 are compared at the numeric comparison circuit 13, and if they are not in agreement, the output g is "1". Further, the transfer instruction detection circuit 12 detects whether the operation control signal c is the transfer instruction or not, and it transfer instruction is detected, the output f is "1". Further, the AND gate 14 detects that the signals g and f are both "1" to output the error detection signal e. In general, since the transfer instruction is much frequently executed, the failure of the arithmetic logical operation unit can be almost be checked by monitoring the error detection signal e.
COPYRIGHT: (C)1980,JPO&Japio
JP12414778A 1978-10-11 1978-10-11 Check system of arithmetic logical operation unit Pending JPS5552155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12414778A JPS5552155A (en) 1978-10-11 1978-10-11 Check system of arithmetic logical operation unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12414778A JPS5552155A (en) 1978-10-11 1978-10-11 Check system of arithmetic logical operation unit

Publications (1)

Publication Number Publication Date
JPS5552155A true JPS5552155A (en) 1980-04-16

Family

ID=14878089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12414778A Pending JPS5552155A (en) 1978-10-11 1978-10-11 Check system of arithmetic logical operation unit

Country Status (1)

Country Link
JP (1) JPS5552155A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57181412U (en) * 1982-04-03 1982-11-17

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57181412U (en) * 1982-04-03 1982-11-17

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