JPS555539A - Ad converter of non-linear quantization - Google Patents

Ad converter of non-linear quantization

Info

Publication number
JPS555539A
JPS555539A JP7838378A JP7838378A JPS555539A JP S555539 A JPS555539 A JP S555539A JP 7838378 A JP7838378 A JP 7838378A JP 7838378 A JP7838378 A JP 7838378A JP S555539 A JPS555539 A JP S555539A
Authority
JP
Japan
Prior art keywords
fed
circuit
signal
compression
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7838378A
Other languages
Japanese (ja)
Inventor
Yuichi Mori
Kengo Sudo
Makoto Iwazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP7838378A priority Critical patent/JPS555539A/en
Publication of JPS555539A publication Critical patent/JPS555539A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To obtain sufficient accuracy without performance requirements in high degree to operational amplifiers and so on, by detecting the level of analog signal before sample hold and performing the next processing through obtaining the presence of necessity for the compression of waveform.
CONSTITUTION: Analog input signal is fed to the analog delay circuit 2 and the voltage comparator 8 via the low pass filter 1, and the signal delayed in the circuit 2 is fed to one terminal a of the electronic switch 4 directly if no compression for the signal delayed in the circuit 2 is requred, and it is fed to another terminal b of the switch 4 after the compression at the resistor attenuator 3 if required. After that, this output is amplified at the amplifier 5, sample-held at the sample hold circuit 6 being into the digital signal at the A/D converter 7 for linear quantization. On the other hand, at the voltage comparator 8, the input signal is compared into a given level, and it is fed to the switch 4 via the OR gate 12 after being latched at the latch circuits 9 to 11. Further, the output of the gate 12 is delayed at the digital delay circuit 13 and outputted to the poststate with the converter 7.
COPYRIGHT: (C)1980,JPO&Japio
JP7838378A 1978-06-27 1978-06-27 Ad converter of non-linear quantization Pending JPS555539A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7838378A JPS555539A (en) 1978-06-27 1978-06-27 Ad converter of non-linear quantization

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7838378A JPS555539A (en) 1978-06-27 1978-06-27 Ad converter of non-linear quantization

Publications (1)

Publication Number Publication Date
JPS555539A true JPS555539A (en) 1980-01-16

Family

ID=13660483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7838378A Pending JPS555539A (en) 1978-06-27 1978-06-27 Ad converter of non-linear quantization

Country Status (1)

Country Link
JP (1) JPS555539A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132021A (en) * 1980-03-19 1981-10-16 Hitachi Ltd Analogue and digital converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132021A (en) * 1980-03-19 1981-10-16 Hitachi Ltd Analogue and digital converter

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