JPS5555680A - Demodulator for synchronizing signal - Google Patents

Demodulator for synchronizing signal

Info

Publication number
JPS5555680A
JPS5555680A JP12780278A JP12780278A JPS5555680A JP S5555680 A JPS5555680 A JP S5555680A JP 12780278 A JP12780278 A JP 12780278A JP 12780278 A JP12780278 A JP 12780278A JP S5555680 A JPS5555680 A JP S5555680A
Authority
JP
Japan
Prior art keywords
signal
dropout
output
demodulator
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12780278A
Other languages
Japanese (ja)
Inventor
Eiju Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Denki Electric Inc
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP12780278A priority Critical patent/JPS5555680A/en
Publication of JPS5555680A publication Critical patent/JPS5555680A/en
Pending legal-status Critical Current

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Landscapes

  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE: To output the synchronizing signal without noise, by removing noise from the detection signal detecting dropout, even with short dropout and long dropout.
CONSTITUTION: The amplitude modulation component of the frequency modulation signal inputted to the input terminal 1 is removed with the limiter circuit 2, it is inputted to the first and second pulse counter type demodulators 12a and 12b, the pulse of a given width and amplitude is outputted to the leading of the signal from the demodulator 12, and the pulse of a given width and amplitude is outputted to the trailing of the signal from the demodulator 12b. The output of the demodulators 12a and 12b is fed to the first and second synchronous separation circuits 10a and 10b to separate the first and second synchronizing signals, the logical sum of the synchronizing signal is taken with the signals fed to the OR circuit 11 through separation, and it is fed to the gate circuit 5 by rejecting noise. Further, the signal at the terminal 1 is inputted and the logical sum with the output of the dropout detector 7 detecting the dropout is taken to output the synchronizing signal removing noise component.
COPYRIGHT: (C)1980,JPO&Japio
JP12780278A 1978-10-19 1978-10-19 Demodulator for synchronizing signal Pending JPS5555680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12780278A JPS5555680A (en) 1978-10-19 1978-10-19 Demodulator for synchronizing signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12780278A JPS5555680A (en) 1978-10-19 1978-10-19 Demodulator for synchronizing signal

Publications (1)

Publication Number Publication Date
JPS5555680A true JPS5555680A (en) 1980-04-23

Family

ID=14969029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12780278A Pending JPS5555680A (en) 1978-10-19 1978-10-19 Demodulator for synchronizing signal

Country Status (1)

Country Link
JP (1) JPS5555680A (en)

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