JPS5557962A - Error detection system - Google Patents

Error detection system

Info

Publication number
JPS5557962A
JPS5557962A JP13080378A JP13080378A JPS5557962A JP S5557962 A JPS5557962 A JP S5557962A JP 13080378 A JP13080378 A JP 13080378A JP 13080378 A JP13080378 A JP 13080378A JP S5557962 A JPS5557962 A JP S5557962A
Authority
JP
Japan
Prior art keywords
circuit
parity
check
data
memory element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13080378A
Other languages
Japanese (ja)
Other versions
JPS6030975B2 (en
Inventor
Shohei Ikehara
Moriyuki Takamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53130803A priority Critical patent/JPS6030975B2/en
Publication of JPS5557962A publication Critical patent/JPS5557962A/en
Publication of JPS6030975B2 publication Critical patent/JPS6030975B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To simplify constitution on the whole by checking an input circuit and output circuit by connecting the input and output of a data processing circuit in common.
CONSTITUTION: Write data WD0WQD7, after being lgiven parity bit P2 by parity generating circuit 4, are stored in write register 1. They are sent from register 1 to memory element 8 and parity/check circuit 9 at the same time by data write clock WCLK and while they are written in memory element 8, a parity check is made. To read data in memory element 8, read data are given parity bit P2 by parity generating circuit/check circuit 9 and then sent to read data register 3, so that a parity check will be done by parity check circuit 7. Therefore, an input-output circuit error can be detected without operating the data processing circuit.
COPYRIGHT: (C)1980,JPO&Japio
JP53130803A 1978-10-24 1978-10-24 Error detection method Expired JPS6030975B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53130803A JPS6030975B2 (en) 1978-10-24 1978-10-24 Error detection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53130803A JPS6030975B2 (en) 1978-10-24 1978-10-24 Error detection method

Publications (2)

Publication Number Publication Date
JPS5557962A true JPS5557962A (en) 1980-04-30
JPS6030975B2 JPS6030975B2 (en) 1985-07-19

Family

ID=15043068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53130803A Expired JPS6030975B2 (en) 1978-10-24 1978-10-24 Error detection method

Country Status (1)

Country Link
JP (1) JPS6030975B2 (en)

Also Published As

Publication number Publication date
JPS6030975B2 (en) 1985-07-19

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