JPS5570997A - Error bit check system for read only memory - Google Patents

Error bit check system for read only memory

Info

Publication number
JPS5570997A
JPS5570997A JP14171878A JP14171878A JPS5570997A JP S5570997 A JPS5570997 A JP S5570997A JP 14171878 A JP14171878 A JP 14171878A JP 14171878 A JP14171878 A JP 14171878A JP S5570997 A JPS5570997 A JP S5570997A
Authority
JP
Japan
Prior art keywords
pulse
rom
read
memory
error bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14171878A
Other languages
Japanese (ja)
Other versions
JPS6130301B2 (en
Inventor
Keiichi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14171878A priority Critical patent/JPS5570997A/en
Publication of JPS5570997A publication Critical patent/JPS5570997A/en
Publication of JPS6130301B2 publication Critical patent/JPS6130301B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To enable to detect the error in the write-in pattern with less number of hardwares, by reading out and comparing the same contents of different address in the area of ROM divided into two with the use of the input 1 pin of ROM.
CONSTITUTION: ROM1 inputs the conditional input signal IN and the clock pulse CP and divided 10, 11 to address direction, and the same content is written in the corresponding address. Further, the output 7 read out with 1 level of pulse CP is set at the register 2 in leading of the inversion pulse and the pulse CP, and the data B read out when the pulse CP is at 0 level, is compared with the set data A of the register 2 at the comparison circuit 5 and error signal 9 is outputted. Thus, the error signal 9 is produced and the output OUT of ROM 1 is delivered to each part in parallel.
COPYRIGHT: (C)1980,JPO&Japio
JP14171878A 1978-11-18 1978-11-18 Error bit check system for read only memory Granted JPS5570997A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14171878A JPS5570997A (en) 1978-11-18 1978-11-18 Error bit check system for read only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14171878A JPS5570997A (en) 1978-11-18 1978-11-18 Error bit check system for read only memory

Publications (2)

Publication Number Publication Date
JPS5570997A true JPS5570997A (en) 1980-05-28
JPS6130301B2 JPS6130301B2 (en) 1986-07-12

Family

ID=15298575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14171878A Granted JPS5570997A (en) 1978-11-18 1978-11-18 Error bit check system for read only memory

Country Status (1)

Country Link
JP (1) JPS5570997A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5844488A (en) * 1981-09-11 1983-03-15 日本電信電話株式会社 Pattern generator
JPS6063651A (en) * 1983-09-17 1985-04-12 Nippon Telegr & Teleph Corp <Ntt> Storage device
JPS61267846A (en) * 1984-11-12 1986-11-27 Nec Corp integrated circuit device with memory
JPS63186350A (en) * 1987-01-28 1988-08-01 Nec Corp pattern generation circuit
JPS6444720U (en) * 1987-09-11 1989-03-17
JP2011154582A (en) * 2010-01-28 2011-08-11 Seiko Epson Corp Integrated circuit device and electronic equipment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5844488A (en) * 1981-09-11 1983-03-15 日本電信電話株式会社 Pattern generator
JPS6063651A (en) * 1983-09-17 1985-04-12 Nippon Telegr & Teleph Corp <Ntt> Storage device
JPS61267846A (en) * 1984-11-12 1986-11-27 Nec Corp integrated circuit device with memory
JPS63186350A (en) * 1987-01-28 1988-08-01 Nec Corp pattern generation circuit
JPS6444720U (en) * 1987-09-11 1989-03-17
JP2011154582A (en) * 2010-01-28 2011-08-11 Seiko Epson Corp Integrated circuit device and electronic equipment

Also Published As

Publication number Publication date
JPS6130301B2 (en) 1986-07-12

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