JPS5563786A - Logic slow/fast circuit in electronic watch - Google Patents

Logic slow/fast circuit in electronic watch

Info

Publication number
JPS5563786A
JPS5563786A JP13692978A JP13692978A JPS5563786A JP S5563786 A JPS5563786 A JP S5563786A JP 13692978 A JP13692978 A JP 13692978A JP 13692978 A JP13692978 A JP 13692978A JP S5563786 A JPS5563786 A JP S5563786A
Authority
JP
Japan
Prior art keywords
logic slow
fast
slow
logic
electronic watch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13692978A
Other languages
Japanese (ja)
Inventor
Hiroyuki Yokoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP13692978A priority Critical patent/JPS5563786A/en
Publication of JPS5563786A publication Critical patent/JPS5563786A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electric Clocks (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE: To reduce power consumption by extending timing period of logic slow/ fast operation.
CONSTITUTION: The logic slow/fast proportion is determined by the information entering the terminal C1WC0. Such information is processed by one-time-per-10- second clocks generated by the delaying flip-flop 38 and read out on the output terminals of the delaying flip-flops 39W42. The outputs from which are compared by the NAND gates 43W45 with the deviders 9W11. When coincidence is found, they are brought to the output terminal of NAND gate 46. The logic slow/fast signal generator 47, 48, 49 are used to set and reset the deviders 9W12 at the intervals of one time per 10 seconds.
COPYRIGHT: (C)1980,JPO&Japio
JP13692978A 1978-11-07 1978-11-07 Logic slow/fast circuit in electronic watch Pending JPS5563786A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13692978A JPS5563786A (en) 1978-11-07 1978-11-07 Logic slow/fast circuit in electronic watch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13692978A JPS5563786A (en) 1978-11-07 1978-11-07 Logic slow/fast circuit in electronic watch

Publications (1)

Publication Number Publication Date
JPS5563786A true JPS5563786A (en) 1980-05-14

Family

ID=15186854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13692978A Pending JPS5563786A (en) 1978-11-07 1978-11-07 Logic slow/fast circuit in electronic watch

Country Status (1)

Country Link
JP (1) JPS5563786A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106595A (en) * 1986-10-23 1988-05-11 Seiko Instr & Electronics Ltd Electronic timepiece

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106595A (en) * 1986-10-23 1988-05-11 Seiko Instr & Electronics Ltd Electronic timepiece

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