JPS55676A - Pulse delay circuit - Google Patents

Pulse delay circuit

Info

Publication number
JPS55676A
JPS55676A JP715079A JP715079A JPS55676A JP S55676 A JPS55676 A JP S55676A JP 715079 A JP715079 A JP 715079A JP 715079 A JP715079 A JP 715079A JP S55676 A JPS55676 A JP S55676A
Authority
JP
Japan
Prior art keywords
circuit
counter
supplied
setting
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP715079A
Other languages
Japanese (ja)
Inventor
Ichiro Kosuge
Shigeru Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP715079A priority Critical patent/JPS55676A/en
Publication of JPS55676A publication Critical patent/JPS55676A/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Abstract

PURPOSE: To realize the setting of an accurate delay time in a digital way by installing the counter which is capable of the digital setting of the division ratio and with no use of the element receiving the temperature effect to the time setting circuit.
CONSTITUTION: Pulse input 6 is supplied to OR circuit 20, inverter circuit 15 and FF circuit 16. Circuit 16 has inversion, and FF circuit 11 turns to "1" to be supplied to circuit 20. Output 8 of circuit 15 opens the gate of AND circuit 21, and clock 9 of fundamental clock generation circuit 19 is supplied to 1/N counter 17. After counting of the clock number, counter 17 delivers FF signal 14 to return to the original state. Circuit 16 is reset by signal 14, and the output of circuit 16 becomes "0". Then the delay completes via circuit 20. In this way, a high stability can be kept for the fundamental clock, accordingly the stability of the delay time being increased.
COPYRIGHT: (C)1980,JPO&Japio
JP715079A 1979-01-26 1979-01-26 Pulse delay circuit Pending JPS55676A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP715079A JPS55676A (en) 1979-01-26 1979-01-26 Pulse delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP715079A JPS55676A (en) 1979-01-26 1979-01-26 Pulse delay circuit

Publications (1)

Publication Number Publication Date
JPS55676A true JPS55676A (en) 1980-01-07

Family

ID=11658034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP715079A Pending JPS55676A (en) 1979-01-26 1979-01-26 Pulse delay circuit

Country Status (1)

Country Link
JP (1) JPS55676A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5721817A (en) * 1980-07-14 1982-02-04 Jeol Ltd Illuminating time control circuit for electron beam exposure device
JPS6461116A (en) * 1987-08-31 1989-03-08 Nec Corp Delay circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5721817A (en) * 1980-07-14 1982-02-04 Jeol Ltd Illuminating time control circuit for electron beam exposure device
JPS6461116A (en) * 1987-08-31 1989-03-08 Nec Corp Delay circuit

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