JPS5566016A - Signal priority level determination circuit - Google Patents

Signal priority level determination circuit

Info

Publication number
JPS5566016A
JPS5566016A JP14025178A JP14025178A JPS5566016A JP S5566016 A JPS5566016 A JP S5566016A JP 14025178 A JP14025178 A JP 14025178A JP 14025178 A JP14025178 A JP 14025178A JP S5566016 A JPS5566016 A JP S5566016A
Authority
JP
Japan
Prior art keywords
rqst
priority level
output
avlb
denoted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14025178A
Other languages
Japanese (ja)
Other versions
JPS5922975B2 (en
Inventor
Osamu Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP53140251A priority Critical patent/JPS5922975B2/en
Publication of JPS5566016A publication Critical patent/JPS5566016A/en
Publication of JPS5922975B2 publication Critical patent/JPS5922975B2/en
Expired legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To make a high-speed operation possible with a simple constituion by a constitution using an element delay for priority level determination.
CONSTITUTION: Request signals are denoted as RQST0, RQST1 and RQST2 in order from the highest-priority level one, and permission signals corresponding to them are denoted as AVLB0, AVLB1 and AVLB2, and a reset signal is denoted as END. If RQST0 and RQST1 are inputted simultaneously when the circuit is reset, an output is generated from AND.OR inverter circuit 11 to inhibit AND gates 15W17, and simultaneously, FF12WFF14 are triggerred; that is, outputs of FF12 and FF13 are inverted, and output bars A and B inhibit gates 16 and 17 assigned to low-priority level signals. Meanwhile, output E of OR gate 18 is generated by outputs of bars B and C to inhibit the input of circuit 11, and therefore, output states of FF12WFF14 are held independently of the state of request signals until END comes.
COPYRIGHT: (C)1980,JPO&Japio
JP53140251A 1978-11-13 1978-11-13 Signal priority determination circuit Expired JPS5922975B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53140251A JPS5922975B2 (en) 1978-11-13 1978-11-13 Signal priority determination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53140251A JPS5922975B2 (en) 1978-11-13 1978-11-13 Signal priority determination circuit

Publications (2)

Publication Number Publication Date
JPS5566016A true JPS5566016A (en) 1980-05-19
JPS5922975B2 JPS5922975B2 (en) 1984-05-30

Family

ID=15264421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53140251A Expired JPS5922975B2 (en) 1978-11-13 1978-11-13 Signal priority determination circuit

Country Status (1)

Country Link
JP (1) JPS5922975B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161719A (en) * 1983-03-07 1984-09-12 Hitachi Ltd Bus occupancy control device
JPS61151767A (en) * 1984-12-20 1986-07-10 ハネウエル・インコーポレーテツド Arbitration circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5068035A (en) * 1973-10-12 1975-06-07
JPS52124829A (en) * 1976-04-12 1977-10-20 Mitsubishi Electric Corp Common buss control circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5068035A (en) * 1973-10-12 1975-06-07
JPS52124829A (en) * 1976-04-12 1977-10-20 Mitsubishi Electric Corp Common buss control circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161719A (en) * 1983-03-07 1984-09-12 Hitachi Ltd Bus occupancy control device
JPS61151767A (en) * 1984-12-20 1986-07-10 ハネウエル・インコーポレーテツド Arbitration circuit

Also Published As

Publication number Publication date
JPS5922975B2 (en) 1984-05-30

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