JPS5660954A - Processing circuit for external control input signal of cpu - Google Patents

Processing circuit for external control input signal of cpu

Info

Publication number
JPS5660954A
JPS5660954A JP13625379A JP13625379A JPS5660954A JP S5660954 A JPS5660954 A JP S5660954A JP 13625379 A JP13625379 A JP 13625379A JP 13625379 A JP13625379 A JP 13625379A JP S5660954 A JPS5660954 A JP S5660954A
Authority
JP
Japan
Prior art keywords
signal
high level
low level
cpu
interruption processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13625379A
Other languages
Japanese (ja)
Inventor
Yutaka Murao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13625379A priority Critical patent/JPS5660954A/en
Publication of JPS5660954A publication Critical patent/JPS5660954A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify circuits of a main CPU body by adding a latch circuit and gate circuit to CPU.
CONSTITUTION: When signal INT rises to a high level and then signal HO' falls to a low level, namely, when the holding and interruption processing function both become effective, timing signal t1 inverts output signal Q2 of FF2 into the high level and output signal Q3 of FF3 into the low level. Therefore, output INTRX of AND gate 4 falls from the high level to the low level a certain time later and the processing request of the interruption processing function is not selected. When timing signal t2 arrives later, output signal HOLD of FF5 is held at the high level and it is supplied to programmable logic array PLA7, so that CPU1 will perform holding processing. Next, when signal HO' is at the high level and INT is at the high level, namely, the processing request of the interruption processing function is generated, signals Q2 and Q3 are both at the low level, and consequently signal INTRX is at the high level, so that CPU1 will perform the interruption processing on arrival of signal t2.
COPYRIGHT: (C)1981,JPO&Japio
JP13625379A 1979-10-22 1979-10-22 Processing circuit for external control input signal of cpu Pending JPS5660954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13625379A JPS5660954A (en) 1979-10-22 1979-10-22 Processing circuit for external control input signal of cpu

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13625379A JPS5660954A (en) 1979-10-22 1979-10-22 Processing circuit for external control input signal of cpu

Publications (1)

Publication Number Publication Date
JPS5660954A true JPS5660954A (en) 1981-05-26

Family

ID=15170852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13625379A Pending JPS5660954A (en) 1979-10-22 1979-10-22 Processing circuit for external control input signal of cpu

Country Status (1)

Country Link
JP (1) JPS5660954A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023747A (en) * 1973-07-02 1975-03-14
JPS53131731A (en) * 1977-04-22 1978-11-16 Hitachi Ltd Interruption circuit for computer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023747A (en) * 1973-07-02 1975-03-14
JPS53131731A (en) * 1977-04-22 1978-11-16 Hitachi Ltd Interruption circuit for computer

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