JPS556674A - Program interruption system - Google Patents

Program interruption system

Info

Publication number
JPS556674A
JPS556674A JP7957378A JP7957378A JPS556674A JP S556674 A JPS556674 A JP S556674A JP 7957378 A JP7957378 A JP 7957378A JP 7957378 A JP7957378 A JP 7957378A JP S556674 A JPS556674 A JP S556674A
Authority
JP
Japan
Prior art keywords
register
circuit
setting register
request signal
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7957378A
Other languages
Japanese (ja)
Inventor
Susumu Inoue
Jiro Osawa
Masakado Maekawa
Isao Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7957378A priority Critical patent/JPS556674A/en
Publication of JPS556674A publication Critical patent/JPS556674A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To simplify interruption operation by providing several condition establishment detecting methods to a data processing system by sending an interruption request signal when several conditions assigned previously are established simultaneously or this condition is established as many times as assigned.
CONSTITUTION: This system is provided with main memory 1, memory address register 2, writing buffer register 3, memory buffer register 4, instruction register 5, etc. Further, this system is equipped with program counter 6, store address setting register 7, data setting register 8, setting register 9 for the number of times, instruction address setting register 10, comparators 11 to 13, plus circuit 14, register 15 for the number of times, comparator circuit 16, AND circuit 17, OR circuit 18, etc. In the above constitution, write information in register 3 is compared with the content of register 8 by using circuit 12 and when the both agree each other, a coincidence signal is sent to circuit 17, thereby sending out an interruption request signal by using circuit 18.
COPYRIGHT: (C)1980,JPO&Japio
JP7957378A 1978-06-30 1978-06-30 Program interruption system Pending JPS556674A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7957378A JPS556674A (en) 1978-06-30 1978-06-30 Program interruption system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7957378A JPS556674A (en) 1978-06-30 1978-06-30 Program interruption system

Publications (1)

Publication Number Publication Date
JPS556674A true JPS556674A (en) 1980-01-18

Family

ID=13693730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7957378A Pending JPS556674A (en) 1978-06-30 1978-06-30 Program interruption system

Country Status (1)

Country Link
JP (1) JPS556674A (en)

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