JPS5724098A - Fault detecting system of buffer memory control circuit - Google Patents
Fault detecting system of buffer memory control circuitInfo
- Publication number
- JPS5724098A JPS5724098A JP9773580A JP9773580A JPS5724098A JP S5724098 A JPS5724098 A JP S5724098A JP 9773580 A JP9773580 A JP 9773580A JP 9773580 A JP9773580 A JP 9773580A JP S5724098 A JPS5724098 A JP S5724098A
- Authority
- JP
- Japan
- Prior art keywords
- coincidence
- address
- buffer memory
- access request
- reserve
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To simply check the state that cannot arise in the normal state to ensure a normal process of data, by detecting the set address of an access request to a buffer memory in both the reserve mode and the release mode. CONSTITUTION:Registers 9-0-9-n hold during the reserve period the set address of an access request to a buffer memory. Comparators 10-0-10-n compare the set addresses with each other. Then a new access request is discontinued or restarted when a coincidence is obtained between a held address and a new access request address. In addition, the following units are provided: a circuit 11 that detects that the coincidence number of the set address is 2; a circuit 12 that detects that no coincidence exists at all; a reserve mode signal gate 14; and a release mode signal gate 15. Then a coincidence among plural set addresses is detected in the reserve mode; and a coincidence of plural set addresses or a perfect dissidence of the set addresses can be detected in the release mode respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55097735A JPS6044707B2 (en) | 1980-07-17 | 1980-07-17 | Fault detection method for buffer memory control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55097735A JPS6044707B2 (en) | 1980-07-17 | 1980-07-17 | Fault detection method for buffer memory control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5724098A true JPS5724098A (en) | 1982-02-08 |
| JPS6044707B2 JPS6044707B2 (en) | 1985-10-04 |
Family
ID=14200146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55097735A Expired JPS6044707B2 (en) | 1980-07-17 | 1980-07-17 | Fault detection method for buffer memory control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6044707B2 (en) |
-
1980
- 1980-07-17 JP JP55097735A patent/JPS6044707B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6044707B2 (en) | 1985-10-04 |
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