JPS556684A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS556684A
JPS556684A JP7959978A JP7959978A JPS556684A JP S556684 A JPS556684 A JP S556684A JP 7959978 A JP7959978 A JP 7959978A JP 7959978 A JP7959978 A JP 7959978A JP S556684 A JPS556684 A JP S556684A
Authority
JP
Japan
Prior art keywords
register
processing system
modules
memory
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7959978A
Other languages
Japanese (ja)
Other versions
JPS60699B2 (en
Inventor
Taisuke Kanda
Masakatsu Sugimoto
Susumu Sawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53079599A priority Critical patent/JPS60699B2/en
Publication of JPS556684A publication Critical patent/JPS556684A/en
Publication of JPS60699B2 publication Critical patent/JPS60699B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To find rapidly a program error by composing the processing system of several kinds of distinct program modules with the same function, a memory unit stored with the program, and processors.
CONSTITUTION: The processing system consists of central processor 1, comparator 2, instruction register 3, control register 4, local memory 5, main memory 6, AND circuits 7 to 11, latch circuits 12 to 14, etc. Further, main memory 6 is provided with diagnostic areas D1 and D2, correct-answer area F, and distinct program modules MA1 and MA2 and in register 3, those modules MA1 and MA2, and initial addresses AD1 and AD2 are stored. In addition, register 4 is provided with error signal bit DPE and mode display bit DP, and memory 5 with processing areas P1 and P2, and input data area I. In this constitution, modules MA1 and MA2 are executed in sequence and results of the both are compared by comparator 2.
COPYRIGHT: (C)1980,JPO&Japio
JP53079599A 1978-06-30 1978-06-30 data processing system Expired JPS60699B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53079599A JPS60699B2 (en) 1978-06-30 1978-06-30 data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53079599A JPS60699B2 (en) 1978-06-30 1978-06-30 data processing system

Publications (2)

Publication Number Publication Date
JPS556684A true JPS556684A (en) 1980-01-18
JPS60699B2 JPS60699B2 (en) 1985-01-09

Family

ID=13694464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53079599A Expired JPS60699B2 (en) 1978-06-30 1978-06-30 data processing system

Country Status (1)

Country Link
JP (1) JPS60699B2 (en)

Also Published As

Publication number Publication date
JPS60699B2 (en) 1985-01-09

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