JPS5568668A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5568668A
JPS5568668A JP14303778A JP14303778A JPS5568668A JP S5568668 A JPS5568668 A JP S5568668A JP 14303778 A JP14303778 A JP 14303778A JP 14303778 A JP14303778 A JP 14303778A JP S5568668 A JPS5568668 A JP S5568668A
Authority
JP
Japan
Prior art keywords
wafer
peripheral edge
blocks
improper
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14303778A
Other languages
Japanese (ja)
Other versions
JPS6226186B2 (en
Inventor
Yoshitaka Kitano
Makoto Terajima
Hiroshi Egawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP14303778A priority Critical patent/JPS5568668A/en
Publication of JPS5568668A publication Critical patent/JPS5568668A/en
Publication of JPS6226186B2 publication Critical patent/JPS6226186B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance the utility efficiency of a circular semiconductor wafer by setting improper portions occurred at the peripheral edge of the wafer at complementary relation when mounting a plurality of blocks having circuit function such as transistors or the like on a bearer by dividing them into two or four segments equally after providing the blocks even on the peripheral edge of the wafer when forming the blocks on the wafer. CONSTITUTION:When a plurality of circuit blocks A each having transistor, resistors and capacitors as circuit functions are formed on a circular semiconductor wafer, a circuit block A improper even in shape is also formed on the peripheral edge of the wafer to be normally abandoned. When the wafer is then divided into two or four segments and the divided wafers B, C are mounted on a bearer 1, the improper circuits A are so arranged and connected to become complementary relation among the divided wafers. Thus, the peripheral edge of the wafer may be used to thereby improve the utility efficiency of the wafer.
JP14303778A 1978-11-20 1978-11-20 Semiconductor device Granted JPS5568668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14303778A JPS5568668A (en) 1978-11-20 1978-11-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14303778A JPS5568668A (en) 1978-11-20 1978-11-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5568668A true JPS5568668A (en) 1980-05-23
JPS6226186B2 JPS6226186B2 (en) 1987-06-08

Family

ID=15329427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14303778A Granted JPS5568668A (en) 1978-11-20 1978-11-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5568668A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5016080A (en) * 1988-10-07 1991-05-14 Exar Corporation Programmable die size continuous array
US5138419A (en) * 1988-06-01 1992-08-11 Fujitsu Limited Wafer scale integration device with dummy chips and relay pads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5138419A (en) * 1988-06-01 1992-08-11 Fujitsu Limited Wafer scale integration device with dummy chips and relay pads
US5016080A (en) * 1988-10-07 1991-05-14 Exar Corporation Programmable die size continuous array

Also Published As

Publication number Publication date
JPS6226186B2 (en) 1987-06-08

Similar Documents

Publication Publication Date Title
DE3070813D1 (en) Self aligned circuit element or component designed as a bipolar transistor in a semiconductor substrate, and process for its production
JPS5350686A (en) Production of semiconductor integrated circuit
JPS5568668A (en) Semiconductor device
JPS51135383A (en) Semiconductor variable capacitance device
JPS542683A (en) Semiconductor chip
JPS52106279A (en) Manufacture of semiconductor ic
JPS5244585A (en) Process for production of semiconductor integrated circuit
JPS53120383A (en) Production of semiconductor device
JPS51123533A (en) Transistor circuit
JPS5215255A (en) Integrated semiconductor logical circuit
JPS52119874A (en) Semi-conductor device
JPS533781A (en) Semiconductor integrated circuit
JPS531471A (en) Manufacture for semiconductor device
JPS5385159A (en) Production of using semiconductor support and semiconductor device usingsemiconductor support
JPS51113478A (en) The manufacturing method of semiconductor device
JPS53119692A (en) Semiconductor logic circuit device
JPS5345982A (en) Manufacture of semiconductor device
JPS52153669A (en) Photo mask of semiconductor integrated circuit
JPS52155982A (en) Semiconductor device
JPS52153668A (en) Photo mask of semiconductor integrated circuit
JPS527684A (en) Integrated semiconductor devices
JPS5250181A (en) Semiconductor integrated circuit device
JPS5387186A (en) Semiconductor ingegrated circuit device
JPS51147968A (en) Method of manufacturing semiconductor device
JPS5297668A (en) Production of semiconductor device