JPS5569858A - Error detection and correction system - Google Patents

Error detection and correction system

Info

Publication number
JPS5569858A
JPS5569858A JP14319778A JP14319778A JPS5569858A JP S5569858 A JPS5569858 A JP S5569858A JP 14319778 A JP14319778 A JP 14319778A JP 14319778 A JP14319778 A JP 14319778A JP S5569858 A JPS5569858 A JP S5569858A
Authority
JP
Japan
Prior art keywords
error
information
bit
syndrome
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14319778A
Other languages
Japanese (ja)
Other versions
JPS5857783B2 (en
Inventor
Shigeo Kaneda
Eiji Fujiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP53143197A priority Critical patent/JPS5857783B2/en
Publication of JPS5569858A publication Critical patent/JPS5569858A/en
Publication of JPS5857783B2 publication Critical patent/JPS5857783B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To make it possible to detect a block error with a slight gate value and also to simplify syndrome decoding process, by providing a detection circuit with a check bit detection circuit, syndrome generating circuit, error detection circuit, syndrome decoding circit, and error correction circuit. CONSTITUTION:Coded information 10 from CPU is inputted to check bit generating circuit 20 to generate check bit 30 and information 10 is added to it to obtain write data 40, which is written into unit 50. Next, information 60 read out from it is applied to syndrome generating circuit 70 to obtain syndrome bit 80, but at this time, information 60 may have an error bit. For the purpose, bit 80 is sent to error detection circuit 90 to signal 140 indicating the existence of the error and also applied to syndrome decoder circuit 100 to generate error-bit-position pointing signal 110; and signals are sent together with information 60 to error correction circuit 120, which generate information 130 with no error.
JP53143197A 1978-11-20 1978-11-20 Error detection and correction method Expired JPS5857783B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53143197A JPS5857783B2 (en) 1978-11-20 1978-11-20 Error detection and correction method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53143197A JPS5857783B2 (en) 1978-11-20 1978-11-20 Error detection and correction method

Publications (2)

Publication Number Publication Date
JPS5569858A true JPS5569858A (en) 1980-05-26
JPS5857783B2 JPS5857783B2 (en) 1983-12-21

Family

ID=15333122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53143197A Expired JPS5857783B2 (en) 1978-11-20 1978-11-20 Error detection and correction method

Country Status (1)

Country Link
JP (1) JPS5857783B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61126826A (en) * 1984-11-22 1986-06-14 Hiroichi Okano Decoder for double length single error correction double error detection read solomon code
JPH0629865A (en) * 1993-03-25 1994-02-04 Hiroichi Okano Decoder of double-length signal error corrected double error detection reed-solomon code

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61126826A (en) * 1984-11-22 1986-06-14 Hiroichi Okano Decoder for double length single error correction double error detection read solomon code
JPH0629865A (en) * 1993-03-25 1994-02-04 Hiroichi Okano Decoder of double-length signal error corrected double error detection reed-solomon code

Also Published As

Publication number Publication date
JPS5857783B2 (en) 1983-12-21

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