JPS556987A - Muting circuit - Google Patents

Muting circuit

Info

Publication number
JPS556987A
JPS556987A JP15464478A JP15464478A JPS556987A JP S556987 A JPS556987 A JP S556987A JP 15464478 A JP15464478 A JP 15464478A JP 15464478 A JP15464478 A JP 15464478A JP S556987 A JPS556987 A JP S556987A
Authority
JP
Japan
Prior art keywords
circuit
logic circuit
fet16
diodes
muting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15464478A
Other languages
Japanese (ja)
Inventor
Hiromi Kusakabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15464478A priority Critical patent/JPS556987A/en
Publication of JPS556987A publication Critical patent/JPS556987A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/34—Muting amplifier when no signal is present

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To ensure an extremely natural muting effect through the circuit switching operation by connecting the AND circuit via mainly the plus control signal to the gate of the FET inserted into the muting circuit. CONSTITUTION:Both the drain and source electrodes of FET16 are connected to signal circuit 10, and each electrode of diodes 28, 30 and 32 are connected en bloc to the gate electrode of FET16. The logic circuit comprising diodes 28, 30 and 32 functions as an AND circuit if the control signal applied to the input terminal of the logic circuit is taken into consideration based mainly on the plus signal. and capacitor 34 connected between the logic circuit and the earth turns on FET16 when the charging voltage produced by the backward current of each diode in the logic circuit reaches the fixed level.
JP15464478A 1978-12-15 1978-12-15 Muting circuit Pending JPS556987A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15464478A JPS556987A (en) 1978-12-15 1978-12-15 Muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15464478A JPS556987A (en) 1978-12-15 1978-12-15 Muting circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP5844373A Division JPS5010508A (en) 1973-05-25 1973-05-25

Publications (1)

Publication Number Publication Date
JPS556987A true JPS556987A (en) 1980-01-18

Family

ID=15588717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15464478A Pending JPS556987A (en) 1978-12-15 1978-12-15 Muting circuit

Country Status (1)

Country Link
JP (1) JPS556987A (en)

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