JPS5570062A - Complementary symmetry circuit - Google Patents

Complementary symmetry circuit

Info

Publication number
JPS5570062A
JPS5570062A JP13490279A JP13490279A JPS5570062A JP S5570062 A JPS5570062 A JP S5570062A JP 13490279 A JP13490279 A JP 13490279A JP 13490279 A JP13490279 A JP 13490279A JP S5570062 A JPS5570062 A JP S5570062A
Authority
JP
Japan
Prior art keywords
voltage
transistors
power source
drain
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13490279A
Other languages
Japanese (ja)
Inventor
Yasoji Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13490279A priority Critical patent/JPS5570062A/en
Publication of JPS5570062A publication Critical patent/JPS5570062A/en
Pending legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To operate this circuit in high voltage, by lowering voltage applied to a drain of FET brought to non-conductive conditions to value not more than avalanche breakdown voltage by utilizing the saturation action regions of FET put between the drain and an output terminal.
CONSTITUTION: p-Channel type first and second transistors 11, 13 and n-channel type third and fourth transistors 12, 14 are connected in series between the first power source terminal VDD1 and the second power source terminal VSS1. The gates of the first transistor 11 and the third transistor 12 are connected in common and used as input terminals, and output is extracted from a common drain region of the second and fourth transistors 13, 14. DC voltage VDD2 located between the first power source voltage and the second power source voltage is applied to the gates of the second and fourth transistors 13, 14.
COPYRIGHT: (C)1980,JPO&Japio
JP13490279A 1979-10-19 1979-10-19 Complementary symmetry circuit Pending JPS5570062A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13490279A JPS5570062A (en) 1979-10-19 1979-10-19 Complementary symmetry circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13490279A JPS5570062A (en) 1979-10-19 1979-10-19 Complementary symmetry circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP5189974A Division JPS5628412B2 (en) 1974-05-10 1974-05-10

Publications (1)

Publication Number Publication Date
JPS5570062A true JPS5570062A (en) 1980-05-27

Family

ID=15139186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13490279A Pending JPS5570062A (en) 1979-10-19 1979-10-19 Complementary symmetry circuit

Country Status (1)

Country Link
JP (1) JPS5570062A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370575A (en) * 1986-09-12 1988-03-30 Sony Corp Mos logic integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370575A (en) * 1986-09-12 1988-03-30 Sony Corp Mos logic integrated circuit

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