JPS5572246A - Crc circuit - Google Patents

Crc circuit

Info

Publication number
JPS5572246A
JPS5572246A JP14513678A JP14513678A JPS5572246A JP S5572246 A JPS5572246 A JP S5572246A JP 14513678 A JP14513678 A JP 14513678A JP 14513678 A JP14513678 A JP 14513678A JP S5572246 A JPS5572246 A JP S5572246A
Authority
JP
Japan
Prior art keywords
crc
read
series
clock signal
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14513678A
Other languages
Japanese (ja)
Other versions
JPS6022770B2 (en
Inventor
Ryozo Maeno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP53145136A priority Critical patent/JPS6022770B2/en
Publication of JPS5572246A publication Critical patent/JPS5572246A/en
Publication of JPS6022770B2 publication Critical patent/JPS6022770B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE: To enable small-scale hardware and firmware to generate a read trigger leading the read timing for CRC characters when a multi-item generator is used which receives a serial input and generates a serial output.
CONSTITUTION: Address ADR from processor unit PU is decoded and 1st register REG2 is selected; and a CRC trigger signal is generated by the output of REG2 and a read pulse from PU to trigger clock generating circuit C for series-parallel conversion, thereby generating a clock signal for series-parallel conversion. On the basis of this clock signal for series-parallel conversion, a multi-item generator output CRC characters, bit by bit, and CRC characters outputted by the generator are converted into parallel data on the basis of the clock signal for S-P conversion. Consequently, REG2 is selected to read parallel-converted CRC characters.
COPYRIGHT: (C)1980,JPO&Japio
JP53145136A 1978-11-24 1978-11-24 CRC circuit Expired JPS6022770B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53145136A JPS6022770B2 (en) 1978-11-24 1978-11-24 CRC circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53145136A JPS6022770B2 (en) 1978-11-24 1978-11-24 CRC circuit

Publications (2)

Publication Number Publication Date
JPS5572246A true JPS5572246A (en) 1980-05-30
JPS6022770B2 JPS6022770B2 (en) 1985-06-04

Family

ID=15378234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53145136A Expired JPS6022770B2 (en) 1978-11-24 1978-11-24 CRC circuit

Country Status (1)

Country Link
JP (1) JPS6022770B2 (en)

Also Published As

Publication number Publication date
JPS6022770B2 (en) 1985-06-04

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