JPS5572256A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5572256A
JPS5572256A JP14627178A JP14627178A JPS5572256A JP S5572256 A JPS5572256 A JP S5572256A JP 14627178 A JP14627178 A JP 14627178A JP 14627178 A JP14627178 A JP 14627178A JP S5572256 A JPS5572256 A JP S5572256A
Authority
JP
Japan
Prior art keywords
input
output
circuit
control
control signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14627178A
Other languages
Japanese (ja)
Other versions
JPS628822B2 (en
Inventor
Tetsuo Kanai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14627178A priority Critical patent/JPS5572256A/en
Publication of JPS5572256A publication Critical patent/JPS5572256A/en
Publication of JPS628822B2 publication Critical patent/JPS628822B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE: To select one of two kind of control signals by a simple constitution by setting the condition for the selection of one of two kind of control signals by FF, and then by providing a processing circuit which receives the output of a selector circuit as a control signal input and the output of FF as a processing condition input.
CONSTITUTION: Selector circuit 2, having two inputs A and B, is so constituted that input A or B will appear at output D in accordance with whether control input C is "1" or "0". Processing circuit 3 is supplied with control signal input S and processing condition input P and output D of selector circuit 2 is connected to this control input S. Further, the output of FF1 is connected to processing condition P and control input C of circuit 2. Consequently FF1 sets the condition where one of two kinds of control signals is selected, and circuit 3 is provided which receives the output of circuit 2 as a control signal input and the output of FF1 as a processing condition input, so that a simple constitution can select one of two kind of control signals.
COPYRIGHT: (C)1980,JPO&Japio
JP14627178A 1978-11-27 1978-11-27 Information processor Granted JPS5572256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14627178A JPS5572256A (en) 1978-11-27 1978-11-27 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14627178A JPS5572256A (en) 1978-11-27 1978-11-27 Information processor

Publications (2)

Publication Number Publication Date
JPS5572256A true JPS5572256A (en) 1980-05-30
JPS628822B2 JPS628822B2 (en) 1987-02-25

Family

ID=15403954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14627178A Granted JPS5572256A (en) 1978-11-27 1978-11-27 Information processor

Country Status (1)

Country Link
JP (1) JPS5572256A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5074948A (en) * 1973-11-02 1975-06-19
JPS50144351A (en) * 1974-05-09 1975-11-20

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5074948A (en) * 1973-11-02 1975-06-19
JPS50144351A (en) * 1974-05-09 1975-11-20

Also Published As

Publication number Publication date
JPS628822B2 (en) 1987-02-25

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