JPS5577082A - Charge level detecting method of charge transfer type semiconductor device - Google Patents
Charge level detecting method of charge transfer type semiconductor deviceInfo
- Publication number
- JPS5577082A JPS5577082A JP14944578A JP14944578A JPS5577082A JP S5577082 A JPS5577082 A JP S5577082A JP 14944578 A JP14944578 A JP 14944578A JP 14944578 A JP14944578 A JP 14944578A JP S5577082 A JPS5577082 A JP S5577082A
- Authority
- JP
- Japan
- Prior art keywords
- charge
- signal
- decision
- semiconductor device
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/34—Digital stores in which the information is moved stepwise, e.g. shift registers using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C19/36—Digital stores in which the information is moved stepwise, e.g. shift registers using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using multistable semiconductor elements
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
PURPOSE:To make it possible to detect the level of CCD charge on a multi-level storage system (MLS), by making a decision on signal charge, read out by different reference charges stored in dummy cells, by comparing them by steps. CONSTITUTION:The levels of output charges of CCD shift register 3 change into Q, (2/3)Q, (1/3Q), 0, etc., according to the bit state of a signal of two bits, etc. Those charges are compared with reference charge (1/2)Q from 2nd dummy cell 6b applied to sense amplifier 4 through multiplexer 5 and amplifier 4 outputs decision signal ''1'' or ''0''. When this decision signal is ''1'', the reference charge applied to amplifier 4 by way of multiplexer 5 becomes (5/6)Q from 1st dummy cell 6a and a similar two-stage decision is made. When ''0'', on the other hand, the similar two-stage decision is made to detect a charge corresponding to the two-bit signal of the CCD charge on the MLS system, so that the memory will increase in density by the MLS system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53149445A JPS599118B2 (en) | 1978-12-01 | 1978-12-01 | Charge level detection method for charge transport type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53149445A JPS599118B2 (en) | 1978-12-01 | 1978-12-01 | Charge level detection method for charge transport type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5577082A true JPS5577082A (en) | 1980-06-10 |
| JPS599118B2 JPS599118B2 (en) | 1984-02-29 |
Family
ID=15475265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53149445A Expired JPS599118B2 (en) | 1978-12-01 | 1978-12-01 | Charge level detection method for charge transport type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS599118B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60136088A (en) * | 1983-12-23 | 1985-07-19 | Hitachi Ltd | Semiconductor multilevel storage device |
| JPS6190392A (en) * | 1984-10-08 | 1986-05-08 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor memory device |
| US6144585A (en) * | 1993-12-28 | 2000-11-07 | Nippon Steel Corporation | Semiconductor storage device for storing three-or multi-valued data in one memory cell |
-
1978
- 1978-12-01 JP JP53149445A patent/JPS599118B2/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60136088A (en) * | 1983-12-23 | 1985-07-19 | Hitachi Ltd | Semiconductor multilevel storage device |
| JPS6190392A (en) * | 1984-10-08 | 1986-05-08 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor memory device |
| US6144585A (en) * | 1993-12-28 | 2000-11-07 | Nippon Steel Corporation | Semiconductor storage device for storing three-or multi-valued data in one memory cell |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS599118B2 (en) | 1984-02-29 |
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