JPS5577096A - Ccd memory drive system - Google Patents

Ccd memory drive system

Info

Publication number
JPS5577096A
JPS5577096A JP15122478A JP15122478A JPS5577096A JP S5577096 A JPS5577096 A JP S5577096A JP 15122478 A JP15122478 A JP 15122478A JP 15122478 A JP15122478 A JP 15122478A JP S5577096 A JPS5577096 A JP S5577096A
Authority
JP
Japan
Prior art keywords
voltage
mode
memory
ccd memory
stand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15122478A
Other languages
Japanese (ja)
Inventor
Kiyohiko Kobayashi
Hiroo Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP15122478A priority Critical patent/JPS5577096A/en
Publication of JPS5577096A publication Critical patent/JPS5577096A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it possible to use a CCD memory at a high speed with low power consumption, by changing operating frequencies and driving voltages in stand-by mode and operation mode.
CONSTITUTION: In stand-by mode, a clock voltage driving CCD memory M is lowered and the memory is driven at the lowest-limit frequency (point D) where operation is possible by this voltage. In operation mode, the clock voltage is increased and it is driven at the highest-limit frequency (point A) where the operation is possible by this voltage. Namely, CCD memory driver circuit 1F converts basic clocks (fmax) and (fmin) from OFF circuit OR into clocks of freuqencies at points A and D and then supplies them to CCD memory M by way of driver D. Then, the clock voltage of memory M is shaped by a transistor, etc., and switch by a voltage switching circuit in accordance with chip selector signal CS. In this way, high speed operation in operation mode and low power consumption in stand-by mode realized.
COPYRIGHT: (C)1980,JPO&Japio
JP15122478A 1978-12-06 1978-12-06 Ccd memory drive system Pending JPS5577096A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15122478A JPS5577096A (en) 1978-12-06 1978-12-06 Ccd memory drive system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15122478A JPS5577096A (en) 1978-12-06 1978-12-06 Ccd memory drive system

Publications (1)

Publication Number Publication Date
JPS5577096A true JPS5577096A (en) 1980-06-10

Family

ID=15513950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15122478A Pending JPS5577096A (en) 1978-12-06 1978-12-06 Ccd memory drive system

Country Status (1)

Country Link
JP (1) JPS5577096A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6069895A (en) * 1983-09-22 1985-04-20 Fujitsu Ltd Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6069895A (en) * 1983-09-22 1985-04-20 Fujitsu Ltd Semiconductor integrated circuit

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