JPS5577169A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5577169A
JPS5577169A JP15803179A JP15803179A JPS5577169A JP S5577169 A JPS5577169 A JP S5577169A JP 15803179 A JP15803179 A JP 15803179A JP 15803179 A JP15803179 A JP 15803179A JP S5577169 A JPS5577169 A JP S5577169A
Authority
JP
Japan
Prior art keywords
layer
threshold value
mask
sio2
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15803179A
Other languages
Japanese (ja)
Inventor
Satoshi Meguro
Tadahisa Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15803179A priority Critical patent/JPS5577169A/en
Publication of JPS5577169A publication Critical patent/JPS5577169A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To increase parastic MOS's threshold value and breakdown strength while maintaining low threshold value for the COMS transistor device without increasing number of processing steps. CONSTITUTION:The p-Well 4 and p<->-layer 5 are formed on an n-type substrate 1 by implanting B-ions and P-ions in succession. And then, poly Si gates 7 and 7' are provided on gate oxide film by making selective etching of openings on SiO2 film 2. p<+>-layer is formed by contacts among p<+>-layers 9 and 10 and the well 4 through SiO2 mask 8'. The layer 9 and 10 are then covered with SiO2 mask 11, and n<+>-layers 12 and 13 are provided in the well 4 and n<+>-layer is provided on the substrate 1 with the layer 7' as the mask. Removing the mask, covering with PSG 14, selectively etching holes and providing Al wiring 15, it is covered with SiO2 film 16. It is possible, in this method, to maintain threshold value voltage of MOS element low in relation to a certain parastic MOS's threshold value voltage and also to heighten pressure resistance between drain and source.
JP15803179A 1979-12-07 1979-12-07 Preparation of semiconductor device Pending JPS5577169A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15803179A JPS5577169A (en) 1979-12-07 1979-12-07 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15803179A JPS5577169A (en) 1979-12-07 1979-12-07 Preparation of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP48034538A Division JPS49123287A (en) 1973-03-28 1973-03-28

Publications (1)

Publication Number Publication Date
JPS5577169A true JPS5577169A (en) 1980-06-10

Family

ID=15662754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15803179A Pending JPS5577169A (en) 1979-12-07 1979-12-07 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5577169A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03159270A (en) * 1989-11-17 1991-07-09 Toshiba Corp Semiconductor device and manufacture thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ELECTRONICS=1971 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03159270A (en) * 1989-11-17 1991-07-09 Toshiba Corp Semiconductor device and manufacture thereof

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