JPS5577255A - Timing correction circuit - Google Patents

Timing correction circuit

Info

Publication number
JPS5577255A
JPS5577255A JP15338978A JP15338978A JPS5577255A JP S5577255 A JPS5577255 A JP S5577255A JP 15338978 A JP15338978 A JP 15338978A JP 15338978 A JP15338978 A JP 15338978A JP S5577255 A JPS5577255 A JP S5577255A
Authority
JP
Japan
Prior art keywords
clock
output
inputted
signal
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15338978A
Other languages
English (en)
Inventor
Tsutomu Iwahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15338978A priority Critical patent/JPS5577255A/ja
Publication of JPS5577255A publication Critical patent/JPS5577255A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP15338978A 1978-12-06 1978-12-06 Timing correction circuit Pending JPS5577255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15338978A JPS5577255A (en) 1978-12-06 1978-12-06 Timing correction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15338978A JPS5577255A (en) 1978-12-06 1978-12-06 Timing correction circuit

Publications (1)

Publication Number Publication Date
JPS5577255A true JPS5577255A (en) 1980-06-10

Family

ID=15561408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15338978A Pending JPS5577255A (en) 1978-12-06 1978-12-06 Timing correction circuit

Country Status (1)

Country Link
JP (1) JPS5577255A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022236A (ja) * 1987-11-30 1990-01-08 Tandem Comput Inc ２段式同期装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022236A (ja) * 1987-11-30 1990-01-08 Tandem Comput Inc ２段式同期装置

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