JPS5578285A - Electronic watch - Google Patents

Electronic watch

Info

Publication number
JPS5578285A
JPS5578285A JP15346978A JP15346978A JPS5578285A JP S5578285 A JPS5578285 A JP S5578285A JP 15346978 A JP15346978 A JP 15346978A JP 15346978 A JP15346978 A JP 15346978A JP S5578285 A JPS5578285 A JP S5578285A
Authority
JP
Japan
Prior art keywords
circuit
memory
output
frequency
initial set
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15346978A
Other languages
Japanese (ja)
Inventor
Hitoshi Ochiai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP15346978A priority Critical patent/JPS5578285A/en
Publication of JPS5578285A publication Critical patent/JPS5578285A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electric Clocks (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE: To reduce the time required for step adjustment, by providing the initial set circuit for memory and selection circuit, input circuit to change the memory output and the selection circuit to select the output of memory.
CONSTITUTION: A number of crystal oscillators are manufactured with a certain objective value for the frequency of the output Q0 of the oscillation circuit 1, and the value is taken as 32768.8Hz. To obtain the frequency dividing rate, 1/327688 according to it, the memory 7 is made for initial set so that the outputs Q71WQ74 can be outputted to the gate circuit 4 with the signal I=1 of the initial set circuit 10. Then, when the frequency of output Q0 is 32768.7Hz, to take the period of the output Q19 of the frequency divider 2 as 10 seconds and deliver it to the display section 3, one pulse is inputted to the memory 7 through the input circuit 6 to make the frequency dividing rate of the circuit 2 as 1/327687 with the signal V of the control circuit 5. When the frequency of output Q0 is 32768.9Hz, after the initial set, 15 pulses are inputted to the memory 7 through the circuit 6 to obtain the frequency dividing rate 1/327689 or required frequency dividing rate is obtained by inputting one pulse from the input circuit 9.
COPYRIGHT: (C)1980,JPO&Japio
JP15346978A 1978-12-11 1978-12-11 Electronic watch Pending JPS5578285A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15346978A JPS5578285A (en) 1978-12-11 1978-12-11 Electronic watch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15346978A JPS5578285A (en) 1978-12-11 1978-12-11 Electronic watch

Publications (1)

Publication Number Publication Date
JPS5578285A true JPS5578285A (en) 1980-06-12

Family

ID=15563241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15346978A Pending JPS5578285A (en) 1978-12-11 1978-12-11 Electronic watch

Country Status (1)

Country Link
JP (1) JPS5578285A (en)

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