JPS5578360A - Parity check system - Google Patents

Parity check system

Info

Publication number
JPS5578360A
JPS5578360A JP15180378A JP15180378A JPS5578360A JP S5578360 A JPS5578360 A JP S5578360A JP 15180378 A JP15180378 A JP 15180378A JP 15180378 A JP15180378 A JP 15180378A JP S5578360 A JPS5578360 A JP S5578360A
Authority
JP
Japan
Prior art keywords
information signal
data
cpu
signal terminal
parity check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15180378A
Other languages
Japanese (ja)
Inventor
Susumu Enokido
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15180378A priority Critical patent/JPS5578360A/en
Publication of JPS5578360A publication Critical patent/JPS5578360A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To make it possible to detect faults with a simple method by connecting a parity check circuit to a data bus and reporting the result of parity check to peripheral devices of a CPU as a preparable information signal and an initial set information signal.
CONSTITUTION: A CPU and memory MEM are connected by address busses ABoW ABj and data busses DBoWDBn, and further, parity check circuit PC and parity bit generation circuit PG are connected to data lines DBoWDBn. When the CPU reads data of MEM, circuit PG outputs a parity bit signal to parity bit information signal terminal P by the signal of write information signal terminal W. By this parity bit signal, data on data lines DBoWDBn are checked on a basis of the signal from read information signal terminal R from the CPU. In case of normal data, peripheral device preparable information signal terminal RDY is turned on; and in case of abnormal data, an anomaly signal is sent to initial set information signal terminal RST.
COPYRIGHT: (C)1980,JPO&Japio
JP15180378A 1978-12-06 1978-12-06 Parity check system Pending JPS5578360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15180378A JPS5578360A (en) 1978-12-06 1978-12-06 Parity check system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15180378A JPS5578360A (en) 1978-12-06 1978-12-06 Parity check system

Publications (1)

Publication Number Publication Date
JPS5578360A true JPS5578360A (en) 1980-06-12

Family

ID=15526634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15180378A Pending JPS5578360A (en) 1978-12-06 1978-12-06 Parity check system

Country Status (1)

Country Link
JP (1) JPS5578360A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5178938A (en) * 1974-12-31 1976-07-09 Sharp Kk Kiokusochino tajushorisochi
JPS5317037A (en) * 1976-07-30 1978-02-16 Hitachi Ltd Memory parity check system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5178938A (en) * 1974-12-31 1976-07-09 Sharp Kk Kiokusochino tajushorisochi
JPS5317037A (en) * 1976-07-30 1978-02-16 Hitachi Ltd Memory parity check system

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