JPS558067A - Manufacture of semiconductor wafer - Google Patents
Manufacture of semiconductor waferInfo
- Publication number
- JPS558067A JPS558067A JP8089478A JP8089478A JPS558067A JP S558067 A JPS558067 A JP S558067A JP 8089478 A JP8089478 A JP 8089478A JP 8089478 A JP8089478 A JP 8089478A JP S558067 A JPS558067 A JP S558067A
- Authority
- JP
- Japan
- Prior art keywords
- layers
- transition
- substrate
- mono
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 230000007704 transition Effects 0.000 abstract 5
- 238000010438 heat treatment Methods 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 238000005530 etching Methods 0.000 abstract 3
- 235000012431 wafers Nutrition 0.000 abstract 2
- 239000013078 crystal Substances 0.000 abstract 1
- 230000002950 deficient Effects 0.000 abstract 1
- 238000005247 gettering Methods 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
PURPOSE: For obtaining the wafers having gettering function, to make etching removal of only the transition layers at the surfaces to be provided with an element with transition expanded over the whole surface of a mono-crystalline semiconductor substrate through heat-treatment after forming work layers on the both sides of said substrate.
CONSTITUTION: Warp work layers 12 and 13 are on the both sides of a mono- crystalline Si wafer 11 by providing crack, mosaic and mono-crystalline layers, each of the latter two on the preceding, thereof, removed up to a thickness of about 70μm by grinding, and almost equalized in thickness to each other by smoothening. Next, transition layers 14 and 15 are formed by distributing transition up to a required depth of said layers 12 and 13 through heat treatment. This can be attained by selecting heating temperature and time. A distribution depth of about 40μm can be developed by 20 min. continuation of 1,000°C heating. Thereafter, said transition layers 14 and 15 with a thickness of about 20μm are left by the about 20μm etching of the both sides of said substrate 11, and said layer 15 on the right side of said substrate 11 is removed by etching. Thereby, the defective crystal having entered manufacture is absorbed to disappear.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8089478A JPS558067A (en) | 1978-07-05 | 1978-07-05 | Manufacture of semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8089478A JPS558067A (en) | 1978-07-05 | 1978-07-05 | Manufacture of semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS558067A true JPS558067A (en) | 1980-01-21 |
Family
ID=13731060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8089478A Pending JPS558067A (en) | 1978-07-05 | 1978-07-05 | Manufacture of semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS558067A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63206043A (en) * | 1987-02-20 | 1988-08-25 | Fujitsu Ltd | Transmittal acknowledgement equipment in loop network |
| JP2002353224A (en) * | 2001-05-23 | 2002-12-06 | Shin Etsu Handotai Co Ltd | Evaluation method of silicon wafer |
-
1978
- 1978-07-05 JP JP8089478A patent/JPS558067A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63206043A (en) * | 1987-02-20 | 1988-08-25 | Fujitsu Ltd | Transmittal acknowledgement equipment in loop network |
| JP2002353224A (en) * | 2001-05-23 | 2002-12-06 | Shin Etsu Handotai Co Ltd | Evaluation method of silicon wafer |
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