JPS5575221A - Manufacturing semiconductor - Google Patents

Manufacturing semiconductor

Info

Publication number
JPS5575221A
JPS5575221A JP14979078A JP14979078A JPS5575221A JP S5575221 A JPS5575221 A JP S5575221A JP 14979078 A JP14979078 A JP 14979078A JP 14979078 A JP14979078 A JP 14979078A JP S5575221 A JPS5575221 A JP S5575221A
Authority
JP
Japan
Prior art keywords
substrate
orientation
caused
crystal plane
oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14979078A
Other languages
Japanese (ja)
Inventor
Toshihiko Osada
Atsuo Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14979078A priority Critical patent/JPS5575221A/en
Publication of JPS5575221A publication Critical patent/JPS5575221A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12—Preparing bulk and homogeneous wafers
    • H10P90/126—Preparing bulk and homogeneous wafers by chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12—Preparing bulk and homogeneous wafers
    • H10P90/14—Preparing bulk and homogeneous wafers by setting crystal orientation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/201—Marks applied to devices, e.g. for alignment or identification located on the periphery of wafers, e.g. orientation notches or lot numbers

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To enhance reliability of a element by aligning the orientation in a crystal plane of a substrate crystal with the direction of semiconductor to be manufactured by using etch pit as a mark, which are caused by thermal-oxidation-excited defect layer formed in a monocrystal semiconductor substrate.
CONSTITUTION: In the case diffusion is performed in an Si monocrystal substrate having a (100) crystal plane, part of the periphery of the substrate is selectively etched after all the surface is thermally oxidized, and etch pit caused by thermal- oxidation-excitation defect laver are formed. The etching is performed for 30W60sec at a normal temperature by using selective-etching liquid prpared by mixing chromic acid and hydrofluoric acid. In this method, a line 1 indicating the orientation of the crystal plane (-110) and a line 2 indicating the orientation (1-10) are generated. Then, the direction of one side of a V-groove provided on the substrate is alinged with said lines, and a V-MOS and the like are manufactured. In this method, uneven thicknesses of oxidized films to be provided in the later process will not be caused and the degradation of a threshold value is not generated.
COPYRIGHT: (C)1980,JPO&Japio
JP14979078A 1978-12-04 1978-12-04 Manufacturing semiconductor Pending JPS5575221A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14979078A JPS5575221A (en) 1978-12-04 1978-12-04 Manufacturing semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14979078A JPS5575221A (en) 1978-12-04 1978-12-04 Manufacturing semiconductor

Publications (1)

Publication Number Publication Date
JPS5575221A true JPS5575221A (en) 1980-06-06

Family

ID=15482764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14979078A Pending JPS5575221A (en) 1978-12-04 1978-12-04 Manufacturing semiconductor

Country Status (1)

Country Link
JP (1) JPS5575221A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60125726U (en) * 1984-02-02 1985-08-24 住友電気工業株式会社 Compound semiconductor mirror wafer
WO2014054228A1 (en) * 2012-10-02 2014-04-10 株式会社デンソー Silicon carbide semiconductor substrate and method for manufacturing same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60125726U (en) * 1984-02-02 1985-08-24 住友電気工業株式会社 Compound semiconductor mirror wafer
WO2014054228A1 (en) * 2012-10-02 2014-04-10 株式会社デンソー Silicon carbide semiconductor substrate and method for manufacturing same
US9269576B2 (en) 2012-10-02 2016-02-23 Denso Corporation Silicon carbide semiconductor substrate and method for manufacturing same

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