JPS558131A - Automatic gain control voltage compensating circuit - Google Patents

Automatic gain control voltage compensating circuit

Info

Publication number
JPS558131A
JPS558131A JP8049678A JP8049678A JPS558131A JP S558131 A JPS558131 A JP S558131A JP 8049678 A JP8049678 A JP 8049678A JP 8049678 A JP8049678 A JP 8049678A JP S558131 A JPS558131 A JP S558131A
Authority
JP
Japan
Prior art keywords
control voltage
properties
fet
drain
gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8049678A
Other languages
Japanese (ja)
Inventor
Satoshi Fukuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Denki Electric Inc
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP8049678A priority Critical patent/JPS558131A/en
Publication of JPS558131A publication Critical patent/JPS558131A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE: To secure an accurate conversion of the control voltage to the gain of the AGC circuit into the linear change characteristics by controlling the drain current of FET via the control voltage and drawing the output corresponding to the drain voltage for aapplication.
CONSTITUTION: The 4-terminal FET containing 1st and 2nd gates G1 and G2 is used for FETQ1 and Q2. In addition to these FET's, the following units are used to constitute the inverter IV: resistors R1 and R2, operational amplifier A and potentiometer RV1 for adjustment of the offset voltage. To secure a conformity with the VGS property of Q1 and Q2 via the inverter IV, control voltage Eg is inverted and then current ID of drain D of Q1 and Q2 is controlled. In this case, the both properties of -30°C (dotted line) and +75°C (solid line) cross each other at the value of ID of about 2.0mA. And the relationship between the both properties varies in the opposite direction to the temperature characteristics of conventional relation ship 40 (Eg=control voltage; G=gain of variable gain circuit) centering on the value of about 2.0mA. Accordingly, properties 50 and 40 are overlapped each other and the middle part of them is drawn out. As a result, the linear characteristics can be obtained.
COPYRIGHT: (C)1980,JPO&Japio
JP8049678A 1978-07-04 1978-07-04 Automatic gain control voltage compensating circuit Pending JPS558131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8049678A JPS558131A (en) 1978-07-04 1978-07-04 Automatic gain control voltage compensating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8049678A JPS558131A (en) 1978-07-04 1978-07-04 Automatic gain control voltage compensating circuit

Publications (1)

Publication Number Publication Date
JPS558131A true JPS558131A (en) 1980-01-21

Family

ID=13719903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8049678A Pending JPS558131A (en) 1978-07-04 1978-07-04 Automatic gain control voltage compensating circuit

Country Status (1)

Country Link
JP (1) JPS558131A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5881743A (en) * 1981-11-09 1983-05-17 House Food Ind Co Ltd Preparation of black tea jelly

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5881743A (en) * 1981-11-09 1983-05-17 House Food Ind Co Ltd Preparation of black tea jelly

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