JPS5582461A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5582461A
JPS5582461A JP15660178A JP15660178A JPS5582461A JP S5582461 A JPS5582461 A JP S5582461A JP 15660178 A JP15660178 A JP 15660178A JP 15660178 A JP15660178 A JP 15660178A JP S5582461 A JPS5582461 A JP S5582461A
Authority
JP
Japan
Prior art keywords
type
transistor
bipolar transistor
mos
flanks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15660178A
Other languages
Japanese (ja)
Other versions
JPS5949702B2 (en
Inventor
Michihiro Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP53156601A priority Critical patent/JPS5949702B2/en
Publication of JPS5582461A publication Critical patent/JPS5582461A/en
Publication of JPS5949702B2 publication Critical patent/JPS5949702B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To prevent thyristor effect while easily forming a bipolar transistor simultaneously on the same substrate, by surrounding a lower portion and the flanks of a transistor by means of walls, in a CMOS. CONSTITUTION:A p-type wall buried layer 12 of a lower portion of an n channel MOS-type transistor and the n-type collector buried layers 30 of a bipolar transistor are made up on a p-type substrate 11, an n-type epitaxial layer 15 is grown, and the walls of the flanks of the n channel MOS-type transistor and the isolation regions 14 of the bipolar transistor are built up by selectively performing p-type high concentration duffusion. A p-twell 16 for the n-type MOS-type transistor is formed into the wall 14, and source, a drain, a gate oxide film, a gate electrode, a base, an emitter, etc. are made up in the same manner as the formation of normal MOS-type transistor and bipolar transistor.
JP53156601A 1978-12-18 1978-12-18 Semiconductor integrated circuit device Expired JPS5949702B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53156601A JPS5949702B2 (en) 1978-12-18 1978-12-18 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53156601A JPS5949702B2 (en) 1978-12-18 1978-12-18 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS5582461A true JPS5582461A (en) 1980-06-21
JPS5949702B2 JPS5949702B2 (en) 1984-12-04

Family

ID=15631305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53156601A Expired JPS5949702B2 (en) 1978-12-18 1978-12-18 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5949702B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58124269A (en) * 1982-01-21 1983-07-23 Nec Corp Method for manufacturing complementary insulated gate field effect semiconductor device
JPS58192359A (en) * 1982-05-07 1983-11-09 Hitachi Ltd semiconductor equipment
JPS6074468A (en) * 1983-09-29 1985-04-26 Fujitsu Ltd Semiconductor device
JPS60140748A (en) * 1983-12-27 1985-07-25 Rohm Co Ltd Semiconductor device
US6570229B1 (en) * 1999-04-19 2003-05-27 Seiko Instruments Inc. Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5098791A (en) * 1973-12-27 1975-08-06

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5098791A (en) * 1973-12-27 1975-08-06

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58124269A (en) * 1982-01-21 1983-07-23 Nec Corp Method for manufacturing complementary insulated gate field effect semiconductor device
JPS58192359A (en) * 1982-05-07 1983-11-09 Hitachi Ltd semiconductor equipment
JPS6074468A (en) * 1983-09-29 1985-04-26 Fujitsu Ltd Semiconductor device
JPS60140748A (en) * 1983-12-27 1985-07-25 Rohm Co Ltd Semiconductor device
US6570229B1 (en) * 1999-04-19 2003-05-27 Seiko Instruments Inc. Semiconductor device

Also Published As

Publication number Publication date
JPS5949702B2 (en) 1984-12-04

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