JPS5582539A - Non-linear ad conversion circuit - Google Patents

Non-linear ad conversion circuit

Info

Publication number
JPS5582539A
JPS5582539A JP15667978A JP15667978A JPS5582539A JP S5582539 A JPS5582539 A JP S5582539A JP 15667978 A JP15667978 A JP 15667978A JP 15667978 A JP15667978 A JP 15667978A JP S5582539 A JPS5582539 A JP S5582539A
Authority
JP
Japan
Prior art keywords
converter
linear
dynamic range
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15667978A
Other languages
Japanese (ja)
Inventor
Masaru Moriyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP15667978A priority Critical patent/JPS5582539A/en
Publication of JPS5582539A publication Critical patent/JPS5582539A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To enable to optimize the dynamic range of the sample hold circuit, with the non-linear amplifying circuits of a plurality different in input versus output characteristics and the A/D conversion circuits of a plurality connecting to them.
CONSTITUTION: Assuming that the operational amplifiers 13,17 are 1,2 at the gain and the non-linear amplifying circuits 14,18 loss the amplifying function with the input more than positive and negative full scales. Further, the upper rank 2-bit of the linear A/D converter 16 is fed to the decoder 21 discriminating whether or not the input analog signal fi exceeds ±0.5 full scale. The output of the decoder 21 is fed to the output register 22, and when the register 22 is in compression operation, only the output signal of the converter 20 is outputted, and if non-compression operation, only the output signal of the converter 16 is outputted. Thus, the dynamic range of the sample hold circuit is optimized to enable to perform A/D conversion wider in the dynamic range with the A/D converter less in the comparison bit.
COPYRIGHT: (C)1980,JPO&Japio
JP15667978A 1978-12-18 1978-12-18 Non-linear ad conversion circuit Pending JPS5582539A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15667978A JPS5582539A (en) 1978-12-18 1978-12-18 Non-linear ad conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15667978A JPS5582539A (en) 1978-12-18 1978-12-18 Non-linear ad conversion circuit

Publications (1)

Publication Number Publication Date
JPS5582539A true JPS5582539A (en) 1980-06-21

Family

ID=15632944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15667978A Pending JPS5582539A (en) 1978-12-18 1978-12-18 Non-linear ad conversion circuit

Country Status (1)

Country Link
JP (1) JPS5582539A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4484669A (en) * 1981-04-25 1984-11-27 Tokico Ltd. Hydraulic damper

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4484669A (en) * 1981-04-25 1984-11-27 Tokico Ltd. Hydraulic damper

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