JPS5583340A - Buffer circuit - Google Patents

Buffer circuit

Info

Publication number
JPS5583340A
JPS5583340A JP16083878A JP16083878A JPS5583340A JP S5583340 A JPS5583340 A JP S5583340A JP 16083878 A JP16083878 A JP 16083878A JP 16083878 A JP16083878 A JP 16083878A JP S5583340 A JPS5583340 A JP S5583340A
Authority
JP
Japan
Prior art keywords
value
truth
capacity
point
value level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16083878A
Other languages
Japanese (ja)
Other versions
JPS6333735B2 (en
Inventor
Masunori Sugimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16083878A priority Critical patent/JPS5583340A/en
Publication of JPS5583340A publication Critical patent/JPS5583340A/en
Publication of JPS6333735B2 publication Critical patent/JPS6333735B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent the charging performance of output load capacity in an operation state from lowering by charging the capacity, connected between the gate electrode and source electrode of MOSFET, in an operation state and then by discharging it in a stand-by state. CONSTITUTION:In an operation state, CE and CE' are held at a truth-value level and NOT-value level respectively and MOSFETs 29 and 30 are ON and OFF respectively. When a NOR value and truth value are inputted to points 11 and 12 respectively and point 34 is held at the NOR-value level, capacity 31 is charged by way of MOSFET29 and since a voltage across capacity 31 is secured even if inputs to points 11 and 12 are inverted to hold point 34 at the truth-value level, MOSFET24 never turns OFF even when a voltage at point 34 increases up to power voltage VDD. As a result, voltage VDD is obtained as the truth-value level at point 34. In a stand-by state, CE and CE' are a NOT value and truth value, and MOSFETs 29 and 30 are OFF and ON respective; and capacity 31 is discharged via MOSFET30 and MOSFET24 turns OFF, so that a gate circuit of MOSFETs 23-25 will be cut off.
JP16083878A 1978-12-19 1978-12-19 Buffer circuit Granted JPS5583340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16083878A JPS5583340A (en) 1978-12-19 1978-12-19 Buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16083878A JPS5583340A (en) 1978-12-19 1978-12-19 Buffer circuit

Publications (2)

Publication Number Publication Date
JPS5583340A true JPS5583340A (en) 1980-06-23
JPS6333735B2 JPS6333735B2 (en) 1988-07-06

Family

ID=15723496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16083878A Granted JPS5583340A (en) 1978-12-19 1978-12-19 Buffer circuit

Country Status (1)

Country Link
JP (1) JPS5583340A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194729A (en) * 1985-11-21 1987-08-27 デイジタル　イクイプメント　コ−ポレ−シヨン Digital switching circuit
JPS6369336U (en) * 1986-10-22 1988-05-10
JPS63214020A (en) * 1987-03-03 1988-09-06 Fuji Electric Co Ltd Cmos circuit for switching

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5166761A (en) * 1974-12-05 1976-06-09 Mitsubishi Electric Corp

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5166761A (en) * 1974-12-05 1976-06-09 Mitsubishi Electric Corp

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194729A (en) * 1985-11-21 1987-08-27 デイジタル　イクイプメント　コ−ポレ−シヨン Digital switching circuit
JPS6369336U (en) * 1986-10-22 1988-05-10
JPS63214020A (en) * 1987-03-03 1988-09-06 Fuji Electric Co Ltd Cmos circuit for switching

Also Published As

Publication number Publication date
JPS6333735B2 (en) 1988-07-06

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