JPS5584089A - Memory access control system - Google Patents

Memory access control system

Info

Publication number
JPS5584089A
JPS5584089A JP15877578A JP15877578A JPS5584089A JP S5584089 A JPS5584089 A JP S5584089A JP 15877578 A JP15877578 A JP 15877578A JP 15877578 A JP15877578 A JP 15877578A JP S5584089 A JPS5584089 A JP S5584089A
Authority
JP
Japan
Prior art keywords
access
register
time
output
refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15877578A
Other languages
Japanese (ja)
Inventor
Yukikazu Kaburayama
Takeshi Masui
Kiyoshi Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15877578A priority Critical patent/JPS5584089A/en
Publication of JPS5584089A publication Critical patent/JPS5584089A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Image Input (AREA)
  • Digital Computer Display Output (AREA)

Abstract

PURPOSE:To secure the output which continues for the fixed cycle regardless of the access discontinuation due to the refresh, by providing the output register in several steps and at the same time adding the time conditions. CONSTITUTION:The read order given from external device 3 is supplied to paired memory control signal generator circuit 2 via input-step register 5. And the data given from memory 1 and read out by the access of circuit 2 is set to register 11A which is one of output-step registers 11B provided in several steps. The next read order is set to register 11B in the same way. In this case, each time is set so as to satisfy Eq. (1), where TR is the time required for the refresh, TA is the time required for the access, T is the timing clock cycle with which the access is given, and n is the access frequency carried out during time TR respectively. In such way, the access is discontinued at the refresh time, but the output synchronizing with the timing clock and also continuous can be obtained from output register 11C of the final step.
JP15877578A 1978-12-19 1978-12-19 Memory access control system Pending JPS5584089A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15877578A JPS5584089A (en) 1978-12-19 1978-12-19 Memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15877578A JPS5584089A (en) 1978-12-19 1978-12-19 Memory access control system

Publications (1)

Publication Number Publication Date
JPS5584089A true JPS5584089A (en) 1980-06-24

Family

ID=15679060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15877578A Pending JPS5584089A (en) 1978-12-19 1978-12-19 Memory access control system

Country Status (1)

Country Link
JP (1) JPS5584089A (en)

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